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feat(lp_io): Add LP_IO support for ESP32H4

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This commit is contained in:
Song Ruo Jing
2025-07-15 21:21:38 +08:00
parent 8886097fe4
commit 63050580f5
14 changed files with 854 additions and 151 deletions
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45
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -18,6 +18,7 @@
#include "esp_log.h"
#include "soc/rtc_io_periph.h"
#include "soc/soc_caps.h"
#include "hal/rtc_io_ll.h"
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
static const char *TAG = "rtcio_test";
@@ -233,6 +234,48 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
ESP_LOGI(TAG, "RTCIO hold test over");
}
#endif //SOC_RTCIO_HOLD_SUPPORTED
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
/*
* test interrupt functionality
*/
TEST_CASE("RTCIO_interrupt_test", "[rtcio]")
{
gpio_num_t test_io = s_test_map[TEST_RTCIO_INTR_PIN_INDEX];
uint32_t rtc_io_idx = rtc_io_number_get(test_io);
TEST_ESP_OK(rtc_gpio_init(test_io));
TEST_ESP_OK(rtc_gpio_set_direction(test_io, RTC_GPIO_MODE_INPUT_OUTPUT));
TEST_ESP_OK(rtc_gpio_set_level(test_io, 0));
rtcio_ll_intr_enable(test_io, GPIO_INTR_HIGH_LEVEL);
int cnt = 0;
while (cnt < TEST_COUNT) {
TEST_ASSERT_EQUAL_INT(cnt % 2, rtc_gpio_get_level(test_io));
TEST_ASSERT_EQUAL_INT(cnt % 2, !!(rtcio_ll_get_interrupt_status() & (1 << rtc_io_idx)));
cnt++;
TEST_ESP_OK(rtc_gpio_set_level(test_io, cnt % 2));
rtcio_ll_clear_interrupt_status(); // since we are testing level-triggered interrupt, we need to clear the status after setting the level back
vTaskDelay(100 / portTICK_PERIOD_MS);
}
TEST_ESP_OK(rtc_gpio_set_level(test_io, 0));
rtcio_ll_intr_enable(test_io, GPIO_INTR_POSEDGE);
cnt = 0;
while (cnt < TEST_COUNT) {
TEST_ESP_OK(rtc_gpio_set_level(test_io, 1));
TEST_ASSERT_EQUAL_INT(1, !!(rtcio_ll_get_interrupt_status() & (1 << rtc_io_idx)));
rtcio_ll_clear_interrupt_status();
TEST_ESP_OK(rtc_gpio_set_level(test_io, 0));
TEST_ASSERT_EQUAL_INT(0, !!(rtcio_ll_get_interrupt_status() & (1 << rtc_io_idx)));
cnt++;
vTaskDelay(100 / portTICK_PERIOD_MS);
}
rtcio_ll_intr_enable(test_io, GPIO_INTR_DISABLE);
TEST_ESP_OK(rtc_gpio_deinit(test_io));
}
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP

20
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -110,6 +110,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
};
#define TEST_RTCIO_INTR_PIN_INDEX 5 // IO5
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO5
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_GPIO_PIN_COUNT 8
@@ -123,6 +124,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
};
#define TEST_RTCIO_INTR_PIN_INDEX 5 // IO12
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO12
#elif CONFIG_IDF_TARGET_ESP32P4
// Has no input-only rtcio pins, all pins support pull-up/down
@@ -146,6 +148,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
};
#define TEST_RTCIO_INTR_PIN_INDEX 2 // IO2
#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
@@ -159,7 +162,22 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
};
#define TEST_RTCIO_INTR_PIN_INDEX 6 // IO6
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 6 // IO6
#elif CONFIG_IDF_TARGET_ESP32H4
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 6
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_0, //GPIO0
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
};
#define TEST_RTCIO_INTR_PIN_INDEX 2 // IO2
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 2 // IO2
#endif
#ifdef __cplusplus