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feat(lp_io): Add LP_IO support for ESP32H4

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This commit is contained in:
Song Ruo Jing
2025-07-15 21:21:38 +08:00
parent 8886097fe4
commit 63050580f5
14 changed files with 854 additions and 151 deletions
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40
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
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@@ -271,6 +271,26 @@ config SOC_GPIO_ETM_TASKS_PER_GROUP
int
default 8
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
int
default 6
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
@@ -279,6 +299,26 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 6
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool
default y
config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_RTCIO_EDGE_WAKE_SUPPORTED
bool
default y
config SOC_I2C_NUM
int
default 2

25
components/soc/esp32h4/include/soc/rtc_io_channel.h Normal file
View File

@@ -0,0 +1,25 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 2
#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 3
#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 4
#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 5

24
components/soc/esp32h4/include/soc/soc_caps.h
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@@ -219,9 +219,14 @@
// Target has the full LP IO subsystem
// On ESP32-H4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 1
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1
// #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 1
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_39)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK (SOC_GPIO_VALID_GPIO_MASK & ~((1ULL<<6) - 1))
@@ -235,12 +240,13 @@
// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX 1 TODO: [ESP32H4] IDF-12361
/*-------------------------- RTCIO CAPS --------------------------------------*/
// #define SOC_RTCIO_PIN_COUNT 6
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 // This macro indicates that the target has separate RTC IOMUX hardware feature,
// // so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
// // when the pins are switched to RTC function.
// #define SOC_RTCIO_HOLD_SUPPORTED 1
// #define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_PIN_COUNT 6
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /*!< This macro indicates that the target has separate RTC IOMUX hardware feature,
so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
when the pins are switched to RTC function. */
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */

144
components/soc/esp32h4/register/soc/lp_gpio_struct.h
View File

@@ -11,30 +11,30 @@ extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of gpio_out register
/** Type of out register
* LP_GPIO output register
*/
typedef union {
struct {
/** gpio_out_data_orig : R/W/WTC; bitpos: [5:0]; default: 0;
/** out_data_orig : R/W/WTC; bitpos: [5:0]; default: 0;
* Configures the output value of LP_GPIO0 ~ 5 output in simple LP_GPIO output mode.
* 0: Low level
* 1: High level
* The value of bit0 ~ bit5 correspond to the output value of LP_GPIO0 ~ LP_GPIO5
* respectively. Bitxx ~ bitxx is invalid.
*/
uint32_t gpio_out_data_orig:6;
uint32_t out_data_orig:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_out_reg_t;
/** Type of gpio_out_w1ts register
/** Type of out_w1ts register
* LP_GPIO output set register
*/
typedef union {
struct {
/** gpio_out_w1ts : WT; bitpos: [5:0]; default: 0;
/** out_w1ts : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to set the output register LP_GPIO_OUT_REG of LP_GPIO0 ~
* LP_GPIO5.
* 0: Not set
@@ -42,18 +42,18 @@ typedef union {
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set LP_GPIO_OUT_REG.
*/
uint32_t gpio_out_w1ts:6;
uint32_t out_w1ts:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_out_w1ts_reg_t;
/** Type of gpio_out_w1tc register
/** Type of out_w1tc register
* LP_GPIO output clear register
*/
typedef union {
struct {
/** gpio_out_w1tc : WT; bitpos: [5:0]; default: 0;
/** out_w1tc : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to clear the output register LP_GPIO_OUT_REG of LP_GPIO0
* ~ LP_GPIO5 output.
* 0: Not clear
@@ -61,35 +61,35 @@ typedef union {
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear LP_GPIO_OUT_REG.
*/
uint32_t gpio_out_w1tc:6;
uint32_t out_w1tc:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_out_w1tc_reg_t;
/** Type of gpio_enable register
/** Type of enable register
* LP_GPIO output enable register
*/
typedef union {
struct {
/** gpio_enable_data : R/W/WTC; bitpos: [5:0]; default: 0;
/** enable_data : R/W/WTC; bitpos: [5:0]; default: 0;
* Configures whether or not to enable the output of LP_GPIO0 ~ LP_GPIO5.
* 0: Not enable
* 1: Enable
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
*/
uint32_t gpio_enable_data:6;
uint32_t enable_data:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_enable_reg_t;
/** Type of gpio_enable_w1ts register
/** Type of enable_w1ts register
* LP_GPIO output enable set register
*/
typedef union {
struct {
/** gpio_enable_w1ts : WT; bitpos: [5:0]; default: 0;
/** enable_w1ts : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to set the output enable register LP_GPIO_ENABLE_REG of
* LP_GPIO0 ~ LP_GPIO5.
* 0: Not set
@@ -97,18 +97,18 @@ typedef union {
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set LP_GPIO_ENABLE_REG.
*/
uint32_t gpio_enable_w1ts:6;
uint32_t enable_w1ts:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_enable_w1ts_reg_t;
/** Type of gpio_enable_w1tc register
/** Type of enable_w1tc register
* LP_GPIO output enable clear register
*/
typedef union {
struct {
/** gpio_enable_w1tc : WT; bitpos: [5:0]; default: 0;
/** enable_w1tc : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to clear the output enable register LP_GPIO_ENABLE_REG of
* LP_GPIO0 ~ LP_GPIO5.
* 0: Not clear
@@ -116,25 +116,25 @@ typedef union {
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear LP_GPIO_ENABLE_REG.
*/
uint32_t gpio_enable_w1tc:6;
uint32_t enable_w1tc:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_enable_w1tc_reg_t;
/** Type of gpio_in register
/** Type of in register
* LP_GPIO input register
*/
typedef union {
struct {
/** gpio_in_data_next : RO; bitpos: [5:0]; default: 0;
/** in_data_next : RO; bitpos: [5:0]; default: 0;
* Represents the input value of LP_GPIO0 ~ LP_GPIO5. Each bit represents a pin input
* value:
* 0: Low level
* 1: High level
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
*/
uint32_t gpio_in_data_next:6;
uint32_t in_data_next:6;
uint32_t reserved_6:26;
};
uint32_t val;
@@ -142,12 +142,12 @@ typedef union {
/** Group: Interrupt Status Registers */
/** Type of gpio_status register
/** Type of status register
* LP_GPIO interrupt status register
*/
typedef union {
struct {
/** gpio_status_interrupt : R/W/WTC; bitpos: [5:0]; default: 0;
/** status_interrupt : R/W/WTC; bitpos: [5:0]; default: 0;
* The interrupt status of LP_GPIO0 ~ LP_GPIO5, can be configured by the software.
*
* - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
@@ -159,18 +159,18 @@ typedef union {
* LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 1 by the software.
*
*/
uint32_t gpio_status_interrupt:6;
uint32_t status_interrupt:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_status_reg_t;
/** Type of gpio_status_w1ts register
/** Type of status_w1ts register
* LP_GPIO interrupt status set register
*/
typedef union {
struct {
/** gpio_status_w1ts : WT; bitpos: [5:0]; default: 0;
/** status_w1ts : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to set the interrupt status register
* LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5.
*
@@ -179,18 +179,18 @@ typedef union {
* LP_GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
* register to set LP_GPIO_STATUS_INTERRUPT.
*/
uint32_t gpio_status_w1ts:6;
uint32_t status_w1ts:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_status_w1ts_reg_t;
/** Type of gpio_status_w1tc register
/** Type of status_w1tc register
* LP_GPIO interrupt status clear register
*/
typedef union {
struct {
/** gpio_status_w1tc : WT; bitpos: [5:0]; default: 0;
/** status_w1tc : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to clear the interrupt status register
* LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5.
*
@@ -199,18 +199,18 @@ typedef union {
* LP_GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
* register to clear LP_GPIO_STATUS_INTERRUPT.
*/
uint32_t gpio_status_w1tc:6;
uint32_t status_w1tc:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_status_w1tc_reg_t;
/** Type of gpio_status_next register
/** Type of status_next register
* LP_GPIO interrupt source register
*/
typedef union {
struct {
/** gpio_status_interrupt_next : RO; bitpos: [5:0]; default: 0;
/** status_interrupt_next : RO; bitpos: [5:0]; default: 0;
* Represents the interrupt source signal of LP_GPIO0 ~ LP_GPIO5.
* Bit0 ~ bit24 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Each bit represents:
@@ -219,7 +219,7 @@ typedef union {
* The interrupt could be rising edge interrupt, falling edge interrupt, level
* sensitive interrupt and any edge interrupt.
*/
uint32_t gpio_status_interrupt_next:6;
uint32_t status_interrupt_next:6;
uint32_t reserved_6:26;
};
uint32_t val;
@@ -227,12 +227,12 @@ typedef union {
/** Group: Pin Configuration Registers */
/** Type of gpio_pinn register
/** Type of pinn register
* LP_GPIOn configuration register
*/
typedef union {
struct {
/** gpio_pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
/** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.
* 0: Not synchronize
@@ -240,14 +240,14 @@ typedef union {
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
uint32_t gpio_pinn_sync2_bypass:2;
/** gpio_pinn_pad_driver : R/W; bitpos: [2]; default: 0;
uint32_t pinn_sync2_bypass:2;
/** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode.
* 0: Normal output
* 1: Open drain output
*/
uint32_t gpio_pinn_pad_driver:1;
/** gpio_pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
uint32_t pinn_pad_driver:1;
/** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.
* 0: Not synchronize
@@ -255,13 +255,13 @@ typedef union {
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
uint32_t gpio_pinn_sync1_bypass:2;
/** gpio_pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0;
uint32_t pinn_sync1_bypass:2;
/** pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0;
* LP_GPIO wakeup clear register.
*/
uint32_t gpio_pinn_edge_wakeup_clr:1;
uint32_t pinn_edge_wakeup_clr:1;
uint32_t reserved_6:1;
/** gpio_pinn_int_type : R/W; bitpos: [9:7]; default: 0;
/** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures LP_GPIO interrupt type.
* 0: LP_GPIO interrupt disabled
* 1: Rising edge trigger
@@ -270,14 +270,14 @@ typedef union {
* 4: Low level trigger
* 5: High level trigger
*/
uint32_t gpio_pinn_int_type:3;
/** gpio_pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
uint32_t pinn_int_type:3;
/** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable LP_GPIO wake-up function.
* 0: Disable
* 1: Enable
* This function only wakes up the CPU from Light-sleep.
*/
uint32_t gpio_pinn_wakeup_enable:1;
uint32_t pinn_wakeup_enable:1;
uint32_t reserved_11:21;
};
uint32_t val;
@@ -285,24 +285,24 @@ typedef union {
/** Group: Output Configuration Registers */
/** Type of gpio_funcn_out_sel_cfg register
/** Type of funcn_out_sel_cfg register
* Configuration register for LP_GPIOn output
*/
typedef union {
struct {
/** gpio_funcn_out_inv_sel : R/W; bitpos: [0]; default: 0;
/** funcn_out_inv_sel : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
uint32_t gpio_funcn_out_inv_sel:1;
uint32_t funcn_out_inv_sel:1;
uint32_t reserved_1:1;
/** gpio_funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0;
/** funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
uint32_t gpio_funcn_oe_inv_sel:1;
uint32_t funcn_oe_inv_sel:1;
uint32_t reserved_3:29;
};
uint32_t val;
@@ -310,17 +310,17 @@ typedef union {
/** Group: Clock Gate Register */
/** Type of gpio_clock_gate register
/** Type of clock_gate register
* LP_GPIO clock gate register
*/
typedef union {
struct {
/** gpio_clk_en : R/W; bitpos: [0]; default: 1;
/** clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether or not to enable clock gate.
* 0: Not enable
* 1: Enable, the clock is free running.
*/
uint32_t gpio_clk_en:1;
uint32_t clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
@@ -328,15 +328,15 @@ typedef union {
/** Group: Version Register */
/** Type of gpio_date register
/** Type of date register
* LP_GPIO version register
*/
typedef union {
struct {
/** gpio_date : R/W; bitpos: [27:0]; default: 37769744;
/** date : R/W; bitpos: [27:0]; default: 37769744;
* Version control register.
*/
uint32_t gpio_date:28;
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
@@ -345,23 +345,23 @@ typedef union {
typedef struct {
uint32_t reserved_000;
volatile lp_gpio_out_reg_t gpio_out;
volatile lp_gpio_out_w1ts_reg_t gpio_out_w1ts;
volatile lp_gpio_out_w1tc_reg_t gpio_out_w1tc;
volatile lp_gpio_enable_reg_t gpio_enable;
volatile lp_gpio_enable_w1ts_reg_t gpio_enable_w1ts;
volatile lp_gpio_enable_w1tc_reg_t gpio_enable_w1tc;
volatile lp_gpio_in_reg_t gpio_in;
volatile lp_gpio_status_reg_t gpio_status;
volatile lp_gpio_status_w1ts_reg_t gpio_status_w1ts;
volatile lp_gpio_status_w1tc_reg_t gpio_status_w1tc;
volatile lp_gpio_status_next_reg_t gpio_status_next;
volatile lp_gpio_pinn_reg_t gpio_pinn[6];
volatile lp_gpio_out_reg_t out;
volatile lp_gpio_out_w1ts_reg_t out_w1ts;
volatile lp_gpio_out_w1tc_reg_t out_w1tc;
volatile lp_gpio_enable_reg_t enable;
volatile lp_gpio_enable_w1ts_reg_t enable_w1ts;
volatile lp_gpio_enable_w1tc_reg_t enable_w1tc;
volatile lp_gpio_in_reg_t in;
volatile lp_gpio_status_reg_t status;
volatile lp_gpio_status_w1ts_reg_t status_w1ts;
volatile lp_gpio_status_w1tc_reg_t status_w1tc;
volatile lp_gpio_status_next_reg_t status_next;
volatile lp_gpio_pinn_reg_t pinn[6];
uint32_t reserved_048[154];
volatile lp_gpio_funcn_out_sel_cfg_reg_t gpio_funcn_out_sel_cfg[6];
volatile lp_gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[6];
uint32_t reserved_2c8[76];
volatile lp_gpio_clock_gate_reg_t gpio_clock_gate;
volatile lp_gpio_date_reg_t gpio_date;
volatile lp_gpio_clock_gate_reg_t clock_gate;
volatile lp_gpio_date_reg_t date;
} lp_gpio_dev_t;
extern lp_gpio_dev_t LP_GPIO;

68
components/soc/esp32h4/register/soc/lp_iomux_struct.h
View File

@@ -11,101 +11,101 @@ extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of io_mux_gpion register
/** Type of gpion register
* LP IO MUX configuration register for LP_GPIOn
*/
typedef union {
struct {
/** io_mux_gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
/** gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of LP_GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_mcu_oe:1;
/** io_mux_gpion_slp_sel : R/W; bitpos: [1]; default: 0;
uint32_t gpion_mcu_oe:1;
/** gpion_slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for LP_GPIOn.
* 0: Not enter
* 1: Enter
*/
uint32_t io_mux_gpion_slp_sel:1;
/** io_mux_gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
uint32_t gpion_slp_sel:1;
/** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of LP_GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_mcu_wpd:1;
/** io_mux_gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
uint32_t gpion_mcu_wpd:1;
/** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of LP_GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_mcu_wpu:1;
/** io_mux_gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
uint32_t gpion_mcu_wpu:1;
/** gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of LP_GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_mcu_ie:1;
/** io_mux_gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
uint32_t gpion_mcu_ie:1;
/** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of LP_GPIOn during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t io_mux_gpion_mcu_drv:2;
/** io_mux_gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
uint32_t gpion_mcu_drv:2;
/** gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of LP_GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_fun_wpd:1;
/** io_mux_gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
uint32_t gpion_fun_wpd:1;
/** gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of LP_GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_fun_wpu:1;
/** io_mux_gpion_fun_ie : R/W; bitpos: [9]; default: 0;
uint32_t gpion_fun_wpu:1;
/** gpion_fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of LP_GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_fun_ie:1;
/** io_mux_gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
uint32_t gpion_fun_ie:1;
/** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of LP_GPIOn.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t io_mux_gpion_fun_drv:2;
/** io_mux_gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
uint32_t gpion_fun_drv:2;
/** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select LP IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
uint32_t io_mux_gpion_mcu_sel:3;
/** io_mux_gpion_filter_en : R/W; bitpos: [15]; default: 0;
uint32_t gpion_mcu_sel:3;
/** gpion_filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_filter_en:1;
/** io_mux_gpion_hys_en : R/W; bitpos: [16]; default: 0;
uint32_t gpion_filter_en:1;
/** gpion_hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* LP_IO_MUX_GPIOn_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_hys_en:1;
/** io_mux_gpion_hys_sel : R/W; bitpos: [17]; default: 0;
uint32_t gpion_hys_en:1;
/** gpion_hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for LP_GPIOn.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of LP_IO_MUX_GPIOn_HYS_EN
*/
uint32_t io_mux_gpion_hys_sel:1;
uint32_t gpion_hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
@@ -113,15 +113,15 @@ typedef union {
/** Group: Version Register */
/** Type of io_mux_date register
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** io_mux_reg_date : R/W; bitpos: [27:0]; default: 37769744;
/** reg_date : R/W; bitpos: [27:0]; default: 37769744;
* Version control register
*/
uint32_t io_mux_reg_date:28;
uint32_t reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
@@ -129,9 +129,9 @@ typedef union {
typedef struct {
volatile lp_io_mux_gpion_reg_t io_mux_gpion[6];
volatile lp_io_mux_gpion_reg_t gpion[6];
uint32_t reserved_018[121];
volatile lp_io_mux_date_reg_t io_mux_date;
volatile lp_io_mux_date_reg_t date;
} lp_iomux_dev_t;
extern lp_iomux_dev_t LP_IO_MUX;

45
components/soc/esp32h4/rtc_io_periph.c
View File

@@ -4,4 +4,47 @@
* SPDX-License-Identifier: Apache-2.0
*/
// TODO: [ESP32H4] IDF-12393
#include "soc/rtc_io_periph.h"
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0
RTCIO_GPIO1_CHANNEL, //GPIO1
RTCIO_GPIO2_CHANNEL, //GPIO2
RTCIO_GPIO3_CHANNEL, //GPIO3
RTCIO_GPIO4_CHANNEL, //GPIO4
RTCIO_GPIO5_CHANNEL, //GPIO5
-1,//GPIO6
-1,//GPIO7
-1,//GPIO8
-1,//GPIO9
-1,//GPIO10
-1,//GPIO11
-1,//GPIO12
-1,//GPIO13
-1,//GPIO14
-1,//GPIO15
-1,//GPIO16
-1,//GPIO17
-1,//GPIO18
-1,//GPIO19
-1,//GPIO20
-1,//GPIO21
-1,//GPIO22
-1,//GPIO23
-1,//GPIO24
-1,//GPIO25
-1,//GPIO26
-1,//GPIO27
-1,//GPIO28
-1,//GPIO29
-1,//GPIO30
-1,//GPIO31
-1,//GPIO32
-1,//GPIO33
-1,//GPIO34
-1,//GPIO35
-1,//GPIO36
-1,//GPIO37
-1,//GPIO38
-1,//GPIO39
};