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feat(lp_io): Add LP_IO support for ESP32H4

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This commit is contained in:
Song Ruo Jing
2025-07-15 21:21:38 +08:00
parent 8886097fe4
commit 63050580f5
14 changed files with 854 additions and 151 deletions
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40
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
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@@ -271,6 +271,26 @@ config SOC_GPIO_ETM_TASKS_PER_GROUP
int
default 8
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
int
default 6
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
@@ -279,6 +299,26 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 6
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool
default y
config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_RTCIO_EDGE_WAKE_SUPPORTED
bool
default y
config SOC_I2C_NUM
int
default 2

25
components/soc/esp32h4/include/soc/rtc_io_channel.h Normal file
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@@ -0,0 +1,25 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 2
#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 3
#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 4
#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 5

24
components/soc/esp32h4/include/soc/soc_caps.h
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@@ -219,9 +219,14 @@
// Target has the full LP IO subsystem
// On ESP32-H4, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 1
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1
// #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 1
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_39)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK (SOC_GPIO_VALID_GPIO_MASK & ~((1ULL<<6) - 1))
@@ -235,12 +240,13 @@
// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX 1 TODO: [ESP32H4] IDF-12361
/*-------------------------- RTCIO CAPS --------------------------------------*/
// #define SOC_RTCIO_PIN_COUNT 6
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 // This macro indicates that the target has separate RTC IOMUX hardware feature,
// // so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
// // when the pins are switched to RTC function.
// #define SOC_RTCIO_HOLD_SUPPORTED 1
// #define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_PIN_COUNT 6
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /*!< This macro indicates that the target has separate RTC IOMUX hardware feature,
so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
when the pins are switched to RTC function. */
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */