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soc: combine xxx_caps.h into one soc_caps.h
During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
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@@ -31,7 +31,7 @@
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#include "esp_rom_efuse.h"
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#include "soc/dport_reg.h"
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#include "soc/efuse_periph.h"
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#include "soc/spi_caps.h"
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#include "soc/soc_caps.h"
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#include "soc/io_mux_reg.h"
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#include "soc/apb_ctrl_reg.h"
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#include "soc/efuse_reg.h"
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@@ -61,7 +61,7 @@ static const char* TAG = "psram";
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#define PSRAM_RESET 0x99
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#define PSRAM_SET_BURST_LEN 0xC0
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#define PSRAM_DEVICE_ID 0x9F
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// ID
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// ID
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#define PSRAM_ID_KGD_M 0xff
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#define PSRAM_ID_KGD_S 8
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#define PSRAM_ID_KGD 0x5d
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@@ -215,7 +215,7 @@ void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
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_psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
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dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
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esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
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WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
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WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
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WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
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