soc: combine xxx_caps.h into one soc_caps.h

During HAL layer refactoring and new chip bringup, we have several caps.h for each part, to reduce the conflicts to minimum. But this is The capabilities headers will be relataive stable once completely written (maybe after the featues are supported by drivers). Now ESP32 and ESP32-S2 drivers are relative stable, making it a good time to combine all these caps.h into one soc_caps.h This cleanup also move HAL config and pin config into separated files, to make the responsibilities of these headers more clear. This is helpful for the stabilities of soc_caps.h because we want to make it public some day.
2025-08-18 07:37:54 +00:00 · 2020-09-10 10:37:58 +08:00
parent bd7fecd396
commit 647dea9395
182 changed files with 1047 additions and 1387 deletions
--- a/components/hal/adc_hal.c
+++ b/components/hal/adc_hal.c
@@ -13,6 +13,7 @@
 // limitations under the License.

 #include "hal/adc_hal.h"
+#include "hal/adc_hal_conf.h"

 void adc_hal_init(void)
 {
--- a/components/hal/cpu_hal.c
+++ b/components/hal/cpu_hal.c
@@ -21,7 +21,7 @@
 #include "hal/cpu_hal.h"
 #include "hal/cpu_types.h"

-#include "soc/cpu_caps.h"
+#include "soc/soc_caps.h"


 #if SOC_CPU_BREAKPOINTS_NUM > 0
--- a/components/hal/esp32/adc_hal.c
+++ b/components/hal/esp32/adc_hal.c
@@ -15,6 +15,7 @@
 // The HAL layer for ADC (common part)

 #include "hal/adc_hal.h"
+#include "hal/adc_hal_conf.h"
 #include "hal/adc_types.h"

 void adc_hal_digi_init(void)
--- a/components/hal/esp32/include/hal/adc_hal_conf.h
+++ b/components/hal/esp32/include/hal/adc_hal_conf.h
@@ -0,0 +1,31 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_ADC1_DATA_INVERT_DEFAULT    (1)
+#define SOC_ADC2_DATA_INVERT_DEFAULT    (1)
+
+#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
+
+#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
+#define SOC_ADC_FSM_START_WAIT_DEFAULT      (SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT)
+#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
+#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (2)
+
+#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
+
+#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
+
+#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT    (16)
--- a/components/hal/esp32/include/hal/can_types.h
+++ b/components/hal/esp32/include/hal/can_types.h
@@ -38,7 +38,7 @@ extern "C" {
 #define CAN_MSG_FLAG_SELF               TWAI_MSG_FLAG_SELF
 #define CAN_MSG_FLAG_DLC_NON_COMP       TWAI_MSG_FLAG_DLC_NON_COMP

-#if (TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
+#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
 #define CAN_TIMING_CONFIG_12_5KBITS()   TWAI_TIMING_CONFIG_12_5KBITS()
 #define CAN_TIMING_CONFIG_16KBITS()     TWAI_TIMING_CONFIG_16KBITS()
 #define CAN_TIMING_CONFIG_20KBITS()     TWAI_TIMING_CONFIG_20KBITS()
--- a/components/hal/esp32/include/hal/cpu_ll.h
+++ b/components/hal/esp32/include/hal/cpu_ll.h
@@ -17,7 +17,7 @@

 #include "esp_attr.h"

-#include "soc/cpu_caps.h"
+#include "soc/soc_caps.h"

 #include "xt_instr_macros.h"
 #include "xtensa/config/specreg.h"
--- a/components/hal/esp32/include/hal/gpio_ll.h
+++ b/components/hal/esp32/include/hal/gpio_ll.h
@@ -35,6 +35,12 @@ extern "C" {
 // Get GPIO hardware instance with giving gpio num
 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)

+#define GPIO_LL_APP_CPU_INTR_ENA      (BIT(0))
+#define GPIO_LL_APP_CPU_NMI_INTR_ENA  (BIT(1))
+#define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(2))
+#define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(3))
+#define GPIO_LL_SDIO_EXT_INTR_ENA     (BIT(4))
+
 /**
  * @brief Enable pull-up on GPIO.
  *
@@ -147,9 +153,9 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
    if (core_id == 0) {
-        hw->pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+        hw->pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
    } else {
-        hw->pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA;     //enable pro cpu intr
+        hw->pin[gpio_num].int_ena = GPIO_LL_APP_CPU_INTR_ENA;     //enable pro cpu intr
    }
 }

--- a/components/hal/esp32/include/hal/i2c_ll.h
+++ b/components/hal/esp32/include/hal/i2c_ll.h
@@ -22,6 +22,8 @@
 extern "C" {
 #endif

+#define I2C_LL_INTR_MASK          (0x3fff) /*!< I2C all interrupt bitmap */
+
 /**
 * @brief I2C hardware cmd register filed.
 */
@@ -42,7 +44,7 @@ typedef union {
 * @brief I2C interrupt event
 */
 typedef enum {
-    I2C_INTR_EVENT_ERR,        
+    I2C_INTR_EVENT_ERR,
    I2C_INTR_EVENT_ARBIT_LOST,   /*!< I2C arbition lost event */
    I2C_INTR_EVENT_NACK,         /*!< I2C NACK event */
    I2C_INTR_EVENT_TOUT,         /*!< I2C time out event */
@@ -329,7 +331,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
 */
 static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 {
-    hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;    
+    hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;
 }

 /**
@@ -342,7 +344,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 */
 static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
 {
-    hw->fifo_conf.rx_fifo_full_thrhd = full_thr;    
+    hw->fifo_conf.rx_fifo_full_thrhd = full_thr;
 }

 /**
@@ -533,7 +535,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
    uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
    for(int i = 0; i < len; i++) {
        WRITE_PERI_REG(fifo_addr, ptr[i]);
-    }   
+    }
 }

 /**
@@ -549,7 +551,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
    for(int i = 0; i < len; i++) {
        ptr[i] = hw->fifo_data.data;
-    }   
+    }
 }

 /**
--- a/components/hal/esp32/include/hal/mcpwm_ll.h
+++ b/components/hal/esp32/include/hal/mcpwm_ll.h
@@ -22,10 +22,10 @@

 #pragma once

+#include "soc/soc_caps.h"
 #include <soc/mcpwm_periph.h>
 #include "soc/mcpwm_periph.h"
 #include "hal/mcpwm_types.h"
-#include "soc/mcpwm_caps.h"
 #include "hal/hal_defs.h"

 #include "esp_types.h"
--- a/components/hal/esp32/include/hal/mpu_ll.h
+++ b/components/hal/esp32/include/hal/mpu_ll.h
@@ -14,7 +14,7 @@

 #include <stdint.h>

-#include "soc/mpu_caps.h"
+#include "soc/soc_caps.h"

 #include "xt_instr_macros.h"

--- a/components/hal/esp32/include/hal/rmt_ll.h
+++ b/components/hal/esp32/include/hal/rmt_ll.h
@@ -19,7 +19,7 @@ extern "C" {

 #include <stdbool.h>
 #include "soc/rmt_struct.h"
-#include "soc/rmt_caps.h"
+#include "soc/soc_caps.h"

 #define RMT_LL_HW_BASE  (&RMT)
 #define RMT_LL_MEM_BASE (&RMTMEM)
--- a/components/hal/esp32/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32/include/hal/rtc_io_ll.h
@@ -25,6 +25,8 @@
 #include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"

+#define RTCIO_LL_PIN_FUNC     0
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -58,7 +60,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
        // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
        SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
        //0:RTC FUNCTION 1,2,3:Reserved
-        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func);
+        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
    } else if (func == RTCIO_FUNC_DIGITAL) {
        CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
    }
--- a/components/hal/esp32/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32/include/hal/touch_sensor_ll.h
@@ -62,7 +62,7 @@ static inline void touch_ll_set_meas_time(uint16_t meas_time)
    //touch sensor measure time= meas_cycle / 8Mhz
    SENS.sar_touch_ctrl1.touch_meas_delay = meas_time;
    //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
-    SENS.sar_touch_ctrl1.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT;
+    SENS.sar_touch_ctrl1.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX;
 }

 /**
--- a/components/hal/esp32/include/hal/twai_ll.h
+++ b/components/hal/esp32/include/hal/twai_ll.h
@@ -331,7 +331,7 @@ static inline uint32_t twai_ll_get_and_clear_intrs(twai_dev_t *hw)
 */
 static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask)
 {
-#if (CONFIG_ESP32_REV_MIN >= 2)
+#if TWAI_BRP_DIV_SUPPORTED
    //ESP32 Rev 2 or later has brp div field. Need to mask it out
    hw->interrupt_enable_reg.val = (hw->interrupt_enable_reg.val & 0x10) | intr_mask;
 #else
@@ -357,8 +357,8 @@ static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask)
 */
 static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling)
 {
-#if (CONFIG_ESP32_REV_MIN >= 2)
-    if (brp > TWAI_BRP_DIV_THRESH) {
+#if TWAI_BRP_DIV_SUPPORTED
+    if (brp > SOC_TWAI_BRP_DIV_THRESH) {
        //Need to set brp_div bit
        hw->interrupt_enable_reg.brp_div = 1;
        brp /= 2;
--- a/components/hal/esp32/include/hal/uart_ll.h
+++ b/components/hal/esp32/include/hal/uart_ll.h
@@ -17,21 +17,24 @@


 #pragma once
-#include "hal/uart_types.h"
 #include "soc/uart_periph.h"
+#include "hal/uart_types.h"

 #ifdef __cplusplus
 extern "C" {
 #endif

 // The default fifo depth
-#define UART_LL_FIFO_DEF_LEN  (UART_FIFO_LEN)
+#define UART_LL_FIFO_DEF_LEN  (SOC_UART_FIFO_LEN)
 // Get UART hardware instance with giving uart num
 #define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (((num) == 1) ? (&UART1) : (&UART2)))

 // The timeout calibration factor when using ref_tick
 #define UART_LL_TOUT_REF_FACTOR_DEFAULT (8)

+#define UART_LL_MIN_WAKEUP_THRESH (2)
+#define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
+
 // Define UART interrupts
 typedef enum {
    UART_INTR_RXFIFO_FULL      = (0x1<<0),
@@ -250,8 +253,8 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
    uint32_t fifo_cnt = hw->status.rxfifo_cnt;
    typeof(hw->mem_rx_status) rx_status = hw->mem_rx_status;
    uint32_t len = 0;
-    
-    // When using DPort to read fifo, fifo_cnt is not credible, we need to calculate the real cnt based on the fifo read and write pointer. 
+
+    // When using DPort to read fifo, fifo_cnt is not credible, we need to calculate the real cnt based on the fifo read and write pointer.
    // When using AHB to read FIFO, we can use fifo_cnt to indicate the data length in fifo.
    if (rx_status.wr_addr > rx_status.rd_addr) {
        len = rx_status.wr_addr - rx_status.rd_addr;
@@ -286,12 +289,12 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
 */
 static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
 {
-    //workaround for hardware issue, when UART stop bit set as 2-bit mode. 
+    //workaround for hardware issue, when UART stop bit set as 2-bit mode.
    if(stop_bit == UART_STOP_BITS_2)  {
        hw->rs485_conf.dl1_en = 1;
        hw->conf0.stop_bit_num = 0x1;
    } else {
-        hw->rs485_conf.dl1_en = 0;   
+        hw->rs485_conf.dl1_en = 0;
        hw->conf0.stop_bit_num = stop_bit;
    }
 }
@@ -306,7 +309,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
 */
 static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
 {
-    //workaround for hardware issue, when UART stop bit set as 2-bit mode. 
+    //workaround for hardware issue, when UART stop bit set as 2-bit mode.
    if(hw->rs485_conf.dl1_en == 1 && hw->conf0.stop_bit_num == 0x1) {
        *stop_bit = UART_STOP_BITS_2;
    } else {
@@ -573,7 +576,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
 */
 static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
 {
-    hw->sleep_conf.active_threshold = wakeup_thrd  - SOC_UART_MIN_WAKEUP_THRESH;
+    hw->sleep_conf.active_threshold = wakeup_thrd  - UART_LL_MIN_WAKEUP_THRESH;
 }

 /**
@@ -715,7 +718,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
 */
 static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
 {
-    return hw->sleep_conf.active_threshold + SOC_UART_MIN_WAKEUP_THRESH;
+    return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
 }

 /**
--- a/components/hal/esp32/touch_sensor_hal.c
+++ b/components/hal/esp32/touch_sensor_hal.c
@@ -20,8 +20,8 @@
 void touch_hal_init(void)
 {
    touch_ll_intr_disable();
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    touch_ll_clear_group_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX, SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
+    touch_ll_clear_group_mask(TOUCH_PAD_BIT_MASK_ALL, TOUCH_PAD_BIT_MASK_ALL);
    touch_ll_set_trigger_mode(TOUCH_TRIGGER_MODE_DEFAULT);
    touch_ll_set_trigger_source(TOUCH_TRIGGER_SOURCE_DEFAULT);
    touch_ll_clear_trigger_status_mask();
--- a/components/hal/esp32s2/adc_hal.c
+++ b/components/hal/esp32s2/adc_hal.c
@@ -16,6 +16,7 @@

 #include "hal/adc_hal.h"
 #include "hal/adc_types.h"
+#include "hal/adc_hal_conf.h"

 /*---------------------------------------------------------------
                    Digital controller setting
--- a/components/hal/esp32s2/cp_dma_hal.c
+++ b/components/hal/esp32s2/cp_dma_hal.c
@@ -12,6 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.

+#include "soc/soc_caps.h"
 #include "hal/cp_dma_hal.h"
 #include "hal/cp_dma_ll.h"

--- a/components/hal/esp32s2/include/hal/adc_hal_conf.h
+++ b/components/hal/esp32s2/include/hal/adc_hal_conf.h
@@ -0,0 +1,31 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_ADC1_DATA_INVERT_DEFAULT    (0)
+#define SOC_ADC2_DATA_INVERT_DEFAULT    (0)
+
+#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
+
+#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
+#define SOC_ADC_FSM_START_WAIT_DEFAULT      (5)
+#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
+#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (3)
+
+#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
+
+#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
+
+#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT    (2)
--- a/components/hal/esp32s2/include/hal/cpu_ll.h
+++ b/components/hal/esp32s2/include/hal/cpu_ll.h
@@ -16,7 +16,7 @@

 #include "esp_attr.h"

-#include "soc/cpu_caps.h"
+#include "soc/soc_caps.h"

 #include "xt_instr_macros.h"
 #include "xtensa/config/specreg.h"
--- a/components/hal/esp32s2/include/hal/gpio_ll.h
+++ b/components/hal/esp32s2/include/hal/gpio_ll.h
@@ -35,6 +35,9 @@ extern "C" {
 // Get GPIO hardware instance with giving gpio num
 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)

+#define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
+#define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+
 /**
  * @brief Enable pull-up on GPIO.
  *
@@ -147,7 +150,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
    if (core_id == 0) {
-        GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+        GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
    }
 }

--- a/components/hal/esp32s2/include/hal/i2c_ll.h
+++ b/components/hal/esp32s2/include/hal/i2c_ll.h
@@ -22,6 +22,8 @@
 extern "C" {
 #endif

+#define I2C_LL_INTR_MASK          (0x1ffff) /*!< I2C all interrupt bitmap */
+
 /**
 * @brief I2C hardware cmd register filed.
 */
@@ -42,7 +44,7 @@ typedef union {
 * @brief I2C interrupt event
 */
 typedef enum {
-    I2C_INTR_EVENT_ERR,        
+    I2C_INTR_EVENT_ERR,
    I2C_INTR_EVENT_ARBIT_LOST,   /*!< I2C arbition lost event */
    I2C_INTR_EVENT_NACK,         /*!< I2C NACK event */
    I2C_INTR_EVENT_TOUT,         /*!< I2C time out event */
@@ -540,7 +542,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
    uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
    for(int i = 0; i < len; i++) {
        WRITE_PERI_REG(fifo_addr, ptr[i]);
-    }   
+    }
 }

 /**
@@ -557,7 +559,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
    uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
    for(int i = 0; i < len; i++) {
        ptr[i] = READ_PERI_REG(fifo_addr);
-    }   
+    }
 }

 /**
--- a/components/hal/esp32s2/include/hal/mpu_ll.h
+++ b/components/hal/esp32s2/include/hal/mpu_ll.h
@@ -14,7 +14,7 @@

 #include <stdint.h>

-#include "soc/mpu_caps.h"
+#include "soc/soc_caps.h"

 #include "xt_instr_macros.h"

--- a/components/hal/esp32s2/include/hal/rmt_ll.h
+++ b/components/hal/esp32s2/include/hal/rmt_ll.h
@@ -18,8 +18,8 @@ extern "C" {
 #endif

 #include <stdbool.h>
+#include "soc/soc_caps.h"
 #include "soc/rmt_struct.h"
-#include "soc/rmt_caps.h"

 #define RMT_LL_HW_BASE  (&RMT)
 #define RMT_LL_MEM_BASE (&RMTMEM)
--- a/components/hal/esp32s2/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32s2/include/hal/rtc_io_ll.h
@@ -25,6 +25,8 @@
 #include "hal/rtc_io_types.h"
 #include "hal/gpio_types.h"

+#define RTCIO_LL_PIN_FUNC     0
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -59,7 +61,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
        // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
        SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
        //0:RTC FUNCTION 1,2,3:Reserved
-        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func);
+        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
    } else if (func == RTCIO_FUNC_DIGITAL) {
        CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
        SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
--- a/components/hal/esp32s2/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32s2/include/hal/touch_sensor_ll.h
@@ -48,7 +48,7 @@ static inline void touch_ll_set_meas_times(uint16_t meas_time)
    //The times of charge and discharge in each measure process of touch channels.
    RTCCNTL.touch_ctrl1.touch_meas_num = meas_time;
    //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
-    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT; //wait volt stable
+    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX; //wait volt stable
 }

 /**
@@ -345,8 +345,8 @@ static inline void touch_ll_get_threshold(touch_pad_t touch_num, uint32_t *thres
 */
 static inline void touch_ll_set_channel_mask(uint16_t enable_mask)
 {
-    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  |= (enable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    SENS.sar_touch_conf.touch_outen |= (enable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  |= (enable_mask & TOUCH_PAD_BIT_MASK_ALL);
+    SENS.sar_touch_conf.touch_outen |= (enable_mask & TOUCH_PAD_BIT_MASK_ALL);
 }

 /**
@@ -359,7 +359,7 @@ static inline void touch_ll_get_channel_mask(uint16_t *enable_mask)
 {
    *enable_mask = SENS.sar_touch_conf.touch_outen \
                   & RTCCNTL.touch_scan_ctrl.touch_scan_pad_map \
-                   & SOC_TOUCH_SENSOR_BIT_MASK_MAX;
+                   & TOUCH_PAD_BIT_MASK_ALL;
 }

 /**
@@ -370,8 +370,8 @@ static inline void touch_ll_get_channel_mask(uint16_t *enable_mask)
 */
 static inline void touch_ll_clear_channel_mask(uint16_t disable_mask)
 {
-    SENS.sar_touch_conf.touch_outen &= ~(disable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  &= ~(disable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    SENS.sar_touch_conf.touch_outen &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
 }

 /**
@@ -659,7 +659,7 @@ static inline void touch_ll_reset_benchmark(touch_pad_t touch_num)
    /* Clear touch channels to initialize the channel value (benchmark, raw_data).
     */
    if (touch_num == TOUCH_PAD_MAX) {
-        SENS.sar_touch_chn_st.touch_channel_clr = SOC_TOUCH_SENSOR_BIT_MASK_MAX;
+        SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_ALL;
    } else {
        SENS.sar_touch_chn_st.touch_channel_clr = (1U << touch_num);
    }
--- a/components/hal/esp32s2/include/hal/uart_ll.h
+++ b/components/hal/esp32s2/include/hal/uart_ll.h
@@ -25,10 +25,13 @@ extern "C" {
 #endif

 // The default fifo depth
-#define UART_LL_FIFO_DEF_LEN  (UART_FIFO_LEN)
+#define UART_LL_FIFO_DEF_LEN  (SOC_UART_FIFO_LEN)
 // Get UART hardware instance with giving uart num
 #define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))

+#define UART_LL_MIN_WAKEUP_THRESH (2)
+#define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
+
 // Define UART interrupts
 typedef enum {
    UART_INTR_RXFIFO_FULL      = (0x1<<0),
@@ -247,7 +250,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
 * @return None.
 */
 static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
-{ 
+{
    hw->conf0.stop_bit_num = stop_bit;
 }

@@ -523,7 +526,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
 */
 static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
 {
-    hw->sleep_conf.active_threshold = wakeup_thrd - SOC_UART_MIN_WAKEUP_THRESH;
+    hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
 }

 /**
@@ -665,7 +668,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
 */
 static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
 {
-    return hw->sleep_conf.active_threshold + SOC_UART_MIN_WAKEUP_THRESH;
+    return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
 }

 /**
--- a/components/hal/esp32s2/systimer_hal.c
+++ b/components/hal/esp32s2/systimer_hal.c
@@ -14,10 +14,10 @@

 #include <sys/param.h>
 #include <assert.h>
+#include "soc/soc_caps.h"
 #include "hal/systimer_hal.h"
 #include "hal/systimer_ll.h"
 #include "hal/systimer_types.h"
-#include "soc/systimer_caps.h"
 #include "soc/rtc.h"

 #define SYSTIMER_TICKS_PER_US (80) // Number of timer ticks per microsecond
--- a/components/hal/esp32s2/touch_sensor_hal.c
+++ b/components/hal/esp32s2/touch_sensor_hal.c
@@ -14,13 +14,14 @@

 // The HAL layer for Touch Sensor (common part)

+#include "soc/soc_pins.h"
 #include "hal/touch_sensor_hal.h"
 #include "hal/touch_sensor_types.h"

 void touch_hal_init(void)
 {
    touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
    touch_ll_clear_trigger_status_mask();
    touch_ll_set_meas_times(TOUCH_PAD_MEASURE_CYCLE_DEFAULT);
    touch_ll_set_sleep_time(TOUCH_PAD_SLEEP_CYCLE_DEFAULT);
@@ -41,7 +42,7 @@ void touch_hal_deinit(void)
    touch_ll_sleep_reset_benchmark();
    touch_ll_stop_fsm();
    touch_ll_clkgate(false);
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
    touch_ll_clear_trigger_status_mask();
    touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
    touch_ll_timeout_disable();
--- a/components/hal/esp32s3/include/hal/adc_hal_conf.h
+++ b/components/hal/esp32s3/include/hal/adc_hal_conf.h
@@ -0,0 +1,31 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_ADC1_DATA_INVERT_DEFAULT    (0)
+#define SOC_ADC2_DATA_INVERT_DEFAULT    (0)
+
+#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
+
+#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
+#define SOC_ADC_FSM_START_WAIT_DEFAULT      (5)
+#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
+#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (2)
+
+#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
+
+#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
+
+#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT     (1)
--- a/components/hal/esp32s3/include/hal/cpu_ll.h
+++ b/components/hal/esp32s3/include/hal/cpu_ll.h
@@ -15,7 +15,7 @@

 #include <stdint.h>

-#include "soc/cpu_caps.h"
+#include "soc/soc_caps.h"

 #include "xt_instr_macros.h"
 #include "xtensa/config/specreg.h"
--- a/components/hal/esp32s3/include/hal/gdma_ll.h
+++ b/components/hal/esp32s3/include/hal/gdma_ll.h
@@ -19,9 +19,9 @@ extern "C" {

 #include <stdint.h>
 #include <stdbool.h>
+#include "soc/soc_caps.h"
 #include "soc/gdma_struct.h"
 #include "soc/gdma_reg.h"
-#include "soc/gdma_caps.h"

 #define GDMA_LL_EVENT_TX_L3_FIFO_UDF (1<<17)
 #define GDMA_LL_EVENT_TX_L3_FIFO_OVF (1<<16)
--- a/components/hal/esp32s3/include/hal/gpio_ll.h
+++ b/components/hal/esp32s3/include/hal/gpio_ll.h
@@ -35,6 +35,9 @@ extern "C" {
 // Get GPIO hardware instance with giving gpio num
 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)

+#define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
+#define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+
 /**
  * @brief Enable pull-up on GPIO.
  *
@@ -147,7 +150,7 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
    if (core_id == 0) {
-        GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+        GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
    }
 }

--- a/components/hal/esp32s3/include/hal/i2c_ll.h
+++ b/components/hal/esp32s3/include/hal/i2c_ll.h
@@ -22,6 +22,8 @@
 extern "C" {
 #endif

+#define I2C_LL_INTR_MASK          (0x3fff) /*!< I2C all interrupt bitmap */
+
 /**
 * @brief I2C hardware cmd register filed.
 */
@@ -42,7 +44,7 @@ typedef union {
 * @brief I2C interrupt event
 */
 typedef enum {
-    I2C_INTR_EVENT_ERR,        
+    I2C_INTR_EVENT_ERR,
    I2C_INTR_EVENT_ARBIT_LOST,   /*!< I2C arbition lost event */
    I2C_INTR_EVENT_NACK,         /*!< I2C NACK event */
    I2C_INTR_EVENT_TOUT,         /*!< I2C time out event */
@@ -329,7 +331,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
 */
 static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 {
-    hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;    
+    hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;
 }

 /**
@@ -342,7 +344,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 */
 static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
 {
-    hw->fifo_conf.rx_fifo_full_thrhd = full_thr;    
+    hw->fifo_conf.rx_fifo_full_thrhd = full_thr;
 }

 /**
@@ -533,7 +535,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
    uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
    for(int i = 0; i < len; i++) {
        WRITE_PERI_REG(fifo_addr, ptr[i]);
-    }   
+    }
 }

 /**
@@ -549,7 +551,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
    for(int i = 0; i < len; i++) {
        ptr[i] = hw->fifo_data.data;
-    }   
+    }
 }

 /**
--- a/components/hal/esp32s3/include/hal/mcpwm_ll.h
+++ b/components/hal/esp32s3/include/hal/mcpwm_ll.h
@@ -22,10 +22,10 @@

 #pragma once

+#include "soc/soc_caps.h"
 #include <soc/mcpwm_periph.h>
 #include "soc/mcpwm_periph.h"
 #include "hal/mcpwm_types.h"
-#include "soc/mcpwm_caps.h"
 #include "hal/hal_defs.h"

 #include "esp_types.h"
--- a/components/hal/esp32s3/include/hal/mpu_ll.h
+++ b/components/hal/esp32s3/include/hal/mpu_ll.h
@@ -14,7 +14,7 @@

 #include <stdint.h>

-#include "soc/mpu_caps.h"
+#include "soc/soc_caps.h"

 #include "xt_instr_macros.h"

--- a/components/hal/esp32s3/include/hal/rmt_ll.h
+++ b/components/hal/esp32s3/include/hal/rmt_ll.h
@@ -20,7 +20,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include "soc/rmt_struct.h"
-#include "soc/rmt_caps.h"
+#include "soc/soc_caps.h"

 #define RMT_LL_HW_BASE  (&RMT)
 #define RMT_LL_MEM_BASE (&RMTMEM)
--- a/components/hal/esp32s3/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32s3/include/hal/rtc_io_ll.h
@@ -59,7 +59,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
        // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
        SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
        //0:RTC FUNCTION 1,2,3:Reserved
-        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func);
+        SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
    } else if (func == RTCIO_FUNC_DIGITAL) {
        CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
        // SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
--- a/components/hal/esp32s3/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32s3/include/hal/touch_sensor_ll.h
@@ -48,7 +48,7 @@ static inline void touch_ll_set_meas_times(uint16_t meas_time)
    //The times of charge and discharge in each measure process of touch channels.
    RTCCNTL.touch_ctrl1.touch_meas_num = meas_time;
    //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
-    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT; //wait volt stable
+    RTCCNTL.touch_ctrl2.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX; //wait volt stable
 }

 /**
@@ -345,8 +345,8 @@ static inline void touch_ll_get_threshold(touch_pad_t touch_num, uint32_t *thres
 */
 static inline void touch_ll_set_channel_mask(uint16_t enable_mask)
 {
-    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  |= (enable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    SENS.sar_touch_conf.touch_outen |= (enable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  |= (enable_mask & TOUCH_PAD_BIT_MASK_ALL);
+    SENS.sar_touch_conf.touch_outen |= (enable_mask & TOUCH_PAD_BIT_MASK_ALL);
 }

 /**
@@ -359,7 +359,7 @@ static inline void touch_ll_get_channel_mask(uint16_t *enable_mask)
 {
    *enable_mask = SENS.sar_touch_conf.touch_outen \
                   & RTCCNTL.touch_scan_ctrl.touch_scan_pad_map \
-                   & SOC_TOUCH_SENSOR_BIT_MASK_MAX;
+                   & TOUCH_PAD_BIT_MASK_ALL;
 }

 /**
@@ -370,8 +370,8 @@ static inline void touch_ll_get_channel_mask(uint16_t *enable_mask)
 */
 static inline void touch_ll_clear_channel_mask(uint16_t disable_mask)
 {
-    SENS.sar_touch_conf.touch_outen &= ~(disable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
-    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  &= ~(disable_mask & SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    SENS.sar_touch_conf.touch_outen &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  &= ~(disable_mask & TOUCH_PAD_BIT_MASK_ALL);
 }

 /**
@@ -659,7 +659,7 @@ static inline void touch_ll_reset_benchmark(touch_pad_t touch_num)
    /* Clear touch channels to initialize the channel value (benchmark, raw_data).
     */
    if (touch_num == TOUCH_PAD_MAX) {
-        SENS.sar_touch_chn_st.touch_channel_clr = SOC_TOUCH_SENSOR_BIT_MASK_MAX;
+        SENS.sar_touch_chn_st.touch_channel_clr = TOUCH_PAD_BIT_MASK_ALL;
    } else {
        SENS.sar_touch_chn_st.touch_channel_clr = (1U << touch_num);
    }
--- a/components/hal/esp32s3/include/hal/twai_ll.h
+++ b/components/hal/esp32s3/include/hal/twai_ll.h
@@ -363,7 +363,7 @@ static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask)
 static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling)
 {
 #ifdef TWAI_BRP_DIV_SUPPORTED
-    if (brp > TWAI_BRP_DIV_THRESH) {
+    if (brp > SOC_TWAI_BRP_DIV_THRESH) {
        //Need to set brp_div bit
        hw->interrupt_enable_reg.brp_div = 1;
        brp /= 2;
--- a/components/hal/esp32s3/include/hal/uart_ll.h
+++ b/components/hal/esp32s3/include/hal/uart_ll.h
@@ -25,10 +25,12 @@ extern "C" {
 #endif

 // The default fifo depth
-#define UART_LL_FIFO_DEF_LEN  (UART_FIFO_LEN)
+#define UART_LL_FIFO_DEF_LEN  (SOC_UART_FIFO_LEN)
 // Get UART hardware instance with giving uart num
 #define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))

+#define UART_LL_MIN_WAKEUP_THRESH (2)
+#define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask

 // Define UART interrupts
 typedef enum {
@@ -521,7 +523,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
 */
 static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
 {
-    hw->sleep_conf.active_threshold = wakeup_thrd - SOC_UART_MIN_WAKEUP_THRESH;
+    hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
 }

 /**
@@ -663,7 +665,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
 */
 static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
 {
-    return hw->sleep_conf.active_threshold + SOC_UART_MIN_WAKEUP_THRESH;
+    return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
 }

 /**
--- a/components/hal/esp32s3/systimer_hal.c
+++ b/components/hal/esp32s3/systimer_hal.c
@@ -13,10 +13,10 @@
 // limitations under the License.

 #include <sys/param.h>
+#include "soc/soc_caps.h"
 #include "hal/systimer_hal.h"
 #include "hal/systimer_ll.h"
 #include "hal/systimer_types.h"
-#include "soc/systimer_caps.h"
 #include "hal/clk_gate_ll.h"

 #define SYSTIMER_TICKS_PER_US  (16) // Systimer clock source is fixed to 16MHz
--- a/components/hal/esp32s3/touch_sensor_hal.c
+++ b/components/hal/esp32s3/touch_sensor_hal.c
@@ -20,7 +20,7 @@
 void touch_hal_init(void)
 {
    touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
    touch_ll_clear_trigger_status_mask();
    touch_ll_set_meas_times(TOUCH_PAD_MEASURE_CYCLE_DEFAULT);
    touch_ll_set_sleep_time(TOUCH_PAD_SLEEP_CYCLE_DEFAULT);
@@ -41,7 +41,7 @@ void touch_hal_deinit(void)
    touch_ll_sleep_reset_benchmark();
    touch_ll_stop_fsm();
    touch_ll_clkgate(false);
-    touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
+    touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
    touch_ll_clear_trigger_status_mask();
    touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
    touch_ll_timeout_disable();
--- a/components/hal/include/hal/adc_types.h
+++ b/components/hal/include/hal/adc_types.h
@@ -16,7 +16,7 @@
 #include <stdbool.h>
 #include <stdint.h>
 #include "sdkconfig.h"
-#include "soc/adc_caps.h"
+#include "soc/soc_caps.h"

 /**
 * @brief ADC unit enumeration.
--- a/components/hal/include/hal/brownout_hal.h
+++ b/components/hal/include/hal/brownout_hal.h
@@ -27,7 +27,7 @@ extern "C" {
 #include <stddef.h>
 #include <stdbool.h>
 #include <stdint.h>
-#include "soc/brownout_caps.h"
+#include "soc/soc_caps.h"

 typedef struct {
    uint8_t threshold;
--- a/components/hal/include/hal/cpu_hal.h
+++ b/components/hal/include/hal/cpu_hal.h
@@ -19,9 +19,9 @@

 #include "esp_err.h"

+#include "soc/soc_caps.h"
 #include "hal/cpu_types.h"
 #include "hal/cpu_ll.h"
-#include "soc/cpu_caps.h"

 #ifdef __cplusplus
 extern "C" {
--- a/components/hal/include/hal/dac_types.h
+++ b/components/hal/include/hal/dac_types.h
@@ -1,6 +1,6 @@
 #pragma once

-#include "soc/dac_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/adc_types.h"
 #include "sdkconfig.h"

--- a/components/hal/include/hal/gpio_hal.h
+++ b/components/hal/include/hal/gpio_hal.h
@@ -319,7 +319,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num);
  */
 #define gpio_hal_iomux_out(hal, gpio_num, func, oen_inv) gpio_ll_iomux_out((hal)->dev, gpio_num, func, oen_inv)

-#if GPIO_SUPPORTS_FORCE_HOLD
+#if SOC_GPIO_SUPPORT_FORCE_HOLD
 /**
  * @brief Force hold digital and rtc gpio pad.
  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
--- a/components/hal/include/hal/gpio_types.h
+++ b/components/hal/include/hal/gpio_types.h
@@ -15,7 +15,7 @@
 #pragma once

 #include "soc/gpio_periph.h"
-#include "soc/gpio_caps.h"
+#include "soc/soc_caps.h"

 #ifdef __cplusplus
 extern "C" {
@@ -70,7 +70,7 @@ typedef enum {
 #define GPIO_SEL_37             ((uint64_t)(((uint64_t)1)<<37))  /*!< Pin 37 selected */
 #define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
 #define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
-#if GPIO_PIN_COUNT > 40
+#if SOC_GPIO_PIN_COUNT > 40
 #define GPIO_SEL_40             ((uint64_t)(((uint64_t)1)<<40))  /*!< Pin 40 selected */
 #define GPIO_SEL_41             ((uint64_t)(((uint64_t)1)<<41))  /*!< Pin 41 selected */
 #define GPIO_SEL_42             ((uint64_t)(((uint64_t)1)<<42))  /*!< Pin 42 selected */
@@ -122,7 +122,7 @@ typedef enum {
 #define GPIO_PIN_REG_37          IO_MUX_GPIO37_REG
 #define GPIO_PIN_REG_38          IO_MUX_GPIO38_REG
 #define GPIO_PIN_REG_39          IO_MUX_GPIO39_REG
-#if GPIO_PIN_COUNT > 40
+#if SOC_GPIO_PIN_COUNT > 40
 #define GPIO_PIN_REG_40          IO_MUX_GPIO40_REG
 #define GPIO_PIN_REG_41          IO_MUX_GPIO41_REG
 #define GPIO_PIN_REG_42          IO_MUX_GPIO42_REG
@@ -179,7 +179,7 @@ typedef enum {
    GPIO_NUM_37 = 37,   /*!< GPIO37, input mode only(ESP32) / input and output(ESP32-S2) */
    GPIO_NUM_38 = 38,   /*!< GPIO38, input mode only(ESP32) / input and output(ESP32-S2) */
    GPIO_NUM_39 = 39,   /*!< GPIO39, input mode only(ESP32) / input and output(ESP32-S2) */
-#if GPIO_PIN_COUNT > 40
+#if SOC_GPIO_PIN_COUNT > 40
    GPIO_NUM_40 = 40,   /*!< GPIO40, input and output */
    GPIO_NUM_41 = 41,   /*!< GPIO41, input and output */
    GPIO_NUM_42 = 42,   /*!< GPIO42, input and output */
@@ -202,6 +202,13 @@ typedef enum {
    GPIO_INTR_MAX,
 } gpio_int_type_t;

+/** @cond */
+#define GPIO_MODE_DEF_DISABLE         (0)
+#define GPIO_MODE_DEF_INPUT           (BIT0)    ///< bit mask for input
+#define GPIO_MODE_DEF_OUTPUT          (BIT1)    ///< bit mask for output
+#define GPIO_MODE_DEF_OD              (BIT2)    ///< bit mask for OD mode
+/** @endcond */
+
 typedef enum {
    GPIO_MODE_DISABLE = GPIO_MODE_DEF_DISABLE,                                                         /*!< GPIO mode : disable input and output             */
    GPIO_MODE_INPUT = GPIO_MODE_DEF_INPUT,                                                             /*!< GPIO mode : input only                           */
--- a/components/hal/include/hal/i2c_types.h
+++ b/components/hal/include/hal/i2c_types.h
@@ -20,7 +20,7 @@ extern "C" {

 #include <stdint.h>
 #include <stdbool.h>
-#include "soc/i2c_caps.h"
+#include "soc/soc_caps.h"

 /**
 * @brief I2C port number, can be I2C_NUM_0 ~ (I2C_NUM_MAX-1).
--- a/components/hal/include/hal/i2s_hal.h
+++ b/components/hal/include/hal/i2s_hal.h
@@ -24,7 +24,7 @@
 #pragma once

 #include "soc/i2s_periph.h"
-#include "soc/i2s_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/i2s_ll.h"
 #include "hal/i2s_types.h"

--- a/components/hal/include/hal/i2s_types.h
+++ b/components/hal/include/hal/i2s_types.h
@@ -17,7 +17,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <stddef.h>
-#include "soc/i2s_caps.h"
+#include "soc/soc_caps.h"

 #ifdef __cplusplus
 extern "C" {
--- a/components/hal/include/hal/ledc_types.h
+++ b/components/hal/include/hal/ledc_types.h
@@ -20,7 +20,7 @@ extern "C" {

 #include <stdint.h>
 #include <stdbool.h>
-#include "soc/ledc_caps.h"
+#include "soc/soc_caps.h"

 typedef enum {
 #ifdef SOC_LEDC_SUPPORT_HS_MODE
--- a/components/hal/include/hal/rmt_hal.h
+++ b/components/hal/include/hal/rmt_hal.h
@@ -18,8 +18,8 @@ extern "C" {
 #endif

 #include <stdint.h>
+#include "soc/soc_caps.h"
 #include "soc/rmt_struct.h"
-#include "soc/rmt_caps.h"

 /**
 * @brief HAL context type of RMT driver
--- a/components/hal/include/hal/rmt_types.h
+++ b/components/hal/include/hal/rmt_types.h
@@ -18,7 +18,7 @@
 extern "C" {
 #endif

-#include "soc/rmt_caps.h"
+#include "soc/soc_caps.h"

 /**
 * @brief RMT channel ID
--- a/components/hal/include/hal/rtc_io_hal.h
+++ b/components/hal/include/hal/rtc_io_hal.h
@@ -33,7 +33,7 @@ extern "C" {
 * Select the rtcio function.
 *
 * @note The RTC function must be selected before the pad analog function is enabled.
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @param func Select pin function.
 */
 #define rtcio_hal_function_select(rtcio_num, func) rtcio_ll_function_select(rtcio_num, func)
@@ -41,21 +41,21 @@ extern "C" {
 /**
 * Enable rtcio output.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_output_enable(rtcio_num) rtcio_ll_output_enable(rtcio_num)

 /**
 * Disable rtcio output.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_output_disable(rtcio_num) rtcio_ll_output_disable(rtcio_num)

 /**
 * Set RTCIO output level.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @param level 0: output low; ~0: output high.
 */
 #define rtcio_hal_set_level(rtcio_num, level) rtcio_ll_set_level(rtcio_num, level)
@@ -63,21 +63,21 @@ extern "C" {
 /**
 * Enable rtcio input.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_input_enable(rtcio_num) rtcio_ll_input_enable(rtcio_num)

 /**
 * Disable rtcio input.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_input_disable(rtcio_num) rtcio_ll_input_disable(rtcio_num)

 /**
 * Get RTCIO input level.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @return 0: input low; ~0: input high.
 */
 #define rtcio_hal_get_level(rtcio_num) rtcio_ll_get_level(rtcio_num)
@@ -85,7 +85,7 @@ extern "C" {
 /**
 * @brief Set RTC GPIO pad drive capability.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @param strength Drive capability of the pad. Range: 0 ~ 3.
 */
 #define rtcio_hal_set_drive_capability(rtcio_num, strength) rtcio_ll_set_drive_capability(rtcio_num, strength)
@@ -93,7 +93,7 @@ extern "C" {
 /**
 * @brief Get RTC GPIO pad drive capability.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @return Drive capability of the pad. Range: 0 ~ 3.
 */
 #define rtcio_hal_get_drive_capability(rtcio_num) rtcio_ll_get_drive_capability(rtcio_num)
@@ -101,7 +101,7 @@ extern "C" {
 /**
 * Set RTCIO output level.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @param level 0: output low; ~0: output high.
 */
 #define rtcio_hal_set_level(rtcio_num, level) rtcio_ll_set_level(rtcio_num, level)
@@ -109,7 +109,7 @@ extern "C" {
 /**
 * Get RTCIO input level.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @return 0: input low; ~0: input high.
 */
 #define rtcio_hal_get_level(rtcio_num) rtcio_ll_get_level(rtcio_num)
@@ -120,7 +120,7 @@ extern "C" {
 * Configure RTC IO direction, such as output only, input only,
 * output and input.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @param mode IO direction.
 */
 void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode);
@@ -131,7 +131,7 @@ void rtcio_hal_set_direction(int rtcio_num, rtc_gpio_mode_t mode);
 * NOTE: ESP32 support INPUT_ONLY mode.
 *       ESP32S2 support INPUT_ONLY, OUTPUT_ONLY, INPUT_OUTPUT mode.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @param mode IO direction.
 */
 void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
@@ -139,28 +139,28 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
 /**
 * RTC GPIO pullup enable.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_pullup_enable(rtcio_num) rtcio_ll_pullup_enable(rtcio_num)

 /**
 * RTC GPIO pullup disable.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_pullup_disable(rtcio_num) rtcio_ll_pullup_disable(rtcio_num)

 /**
 * RTC GPIO pulldown enable.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_pulldown_enable(rtcio_num) rtcio_ll_pulldown_enable(rtcio_num)

 /**
 * RTC GPIO pulldown disable.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_pulldown_disable(rtcio_num) rtcio_ll_pulldown_disable(rtcio_num)

@@ -172,7 +172,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
 * This function is useful when going into light or deep sleep mode to prevent
 * the pin configuration from changing.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_hold_enable(rtcio_num) rtcio_ll_force_hold_enable(rtcio_num)

@@ -180,7 +180,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
 * Disable hold function on an RTC IO pad
 *
 * @note If disable the pad hold, the status of pad maybe changed in sleep mode.
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_hold_disable(rtcio_num) rtcio_ll_force_hold_disable(rtcio_num)

@@ -192,7 +192,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
 * This function is useful when going into light or deep sleep mode to prevent
 * the pin configuration from changing.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_hold_all() rtcio_ll_force_hold_all()

@@ -200,14 +200,14 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
 * Disable hold function on an RTC IO pads.
 *
 * @note If disable the pad hold, the status of pad maybe changed in sleep mode.
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_unhold_all() rtcio_ll_force_unhold_all()

 /**
 * Enable wakeup function and set wakeup type from light sleep status for rtcio.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 * @param type  Wakeup on high level or low level.
 */
 #define rtcio_hal_wakeup_enable(rtcio_num, type) rtcio_ll_wakeup_enable(rtcio_num, type)
@@ -215,14 +215,14 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
 /**
 * Disable wakeup function from light sleep status for rtcio.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_wakeup_disable(rtcio_num) rtcio_ll_wakeup_disable(rtcio_num)

 /**
 * Disable wakeup function from light sleep status for rtcio.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 #define rtcio_hal_ext0_set_wakeup_pin(rtcio_num, level)     rtcio_ll_ext0_set_wakeup_pin(rtcio_num, level)

@@ -237,7 +237,7 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
 * rtc_gpio_isolate(GPIO_NUM_12) before entering deep sleep, to reduce
 * deep sleep current.
 *
- * @param rtcio_num The index of rtcio. 0 ~ SOC_RTC_IO_PIN_COUNT.
+ * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
 */
 void rtcio_hal_isolate(int rtc_num);

--- a/components/hal/include/hal/sigmadelta_types.h
+++ b/components/hal/include/hal/sigmadelta_types.h
@@ -14,7 +14,7 @@

 #pragma once

-#include "soc/sigmadelta_caps.h"
+#include "soc/soc_caps.h"

 #ifdef __cplusplus
 extern "C" {
@@ -23,12 +23,27 @@ extern "C" {
 /**
 * @brief SIGMADELTA port number, the max port number is (SIGMADELTA_NUM_MAX -1).
 */
-typedef int sigmadelta_port_t;
+typedef enum {
+    SIGMADELTA_PORT_0,      /*!< SIGMADELTA port 0 */
+    SIGMADELTA_PORT_MAX,    /*!< SIGMADELTA port max */
+} sigmadelta_port_t;
+
+_Static_assert(SIGMADELTA_PORT_MAX == SOC_SIGMADELTA_NUM, "Sigma-delta port num incorrect.");

 /**
 * @brief Sigma-delta channel list
 */
-typedef int sigmadelta_channel_t;
+typedef enum {
+    SIGMADELTA_CHANNEL_0,   /*!< Sigma-delta channel 0 */
+    SIGMADELTA_CHANNEL_1,   /*!< Sigma-delta channel 1 */
+    SIGMADELTA_CHANNEL_2,   /*!< Sigma-delta channel 2 */
+    SIGMADELTA_CHANNEL_3,   /*!< Sigma-delta channel 3 */
+    SIGMADELTA_CHANNEL_4,   /*!< Sigma-delta channel 4 */
+    SIGMADELTA_CHANNEL_5,   /*!< Sigma-delta channel 5 */
+    SIGMADELTA_CHANNEL_6,   /*!< Sigma-delta channel 6 */
+    SIGMADELTA_CHANNEL_7,   /*!< Sigma-delta channel 7 */
+    SIGMADELTA_CHANNEL_MAX, /*!< Sigma-delta channel max */
+} sigmadelta_channel_t;

 /**
 * @brief Sigma-delta configure struct
--- a/components/hal/include/hal/spi_slave_hal.h
+++ b/components/hal/include/hal/spi_slave_hal.h
@@ -32,10 +32,10 @@

 #pragma once

+#include <esp_types.h>
 #include "soc/lldesc.h"
 #include "soc/spi_struct.h"
-#include <esp_types.h>
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/spi_ll.h"

 /**
--- a/components/hal/include/hal/spi_types.h
+++ b/components/hal/include/hal/spi_types.h
@@ -14,10 +14,10 @@

 #pragma once

-#include "soc/spi_caps.h"
 #include "esp_attr.h"
-#include "sdkconfig.h"
 #include <esp_bit_defs.h>
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"

 /**
 * @brief Enum with the three SPI peripherals that are software-accessible in it
--- a/components/hal/include/hal/systimer_types.h
+++ b/components/hal/include/hal/systimer_types.h
@@ -19,7 +19,7 @@ extern "C" {
 #endif

 #include <stdint.h>
-#include "soc/systimer_caps.h"
+#include "soc/soc_caps.h"

 /*
 * @brief The structure of the counter value in systimer
--- a/components/hal/include/hal/timer_hal.h
+++ b/components/hal/include/hal/timer_hal.h
@@ -27,9 +27,9 @@
 extern "C" {
 #endif

+#include "soc/soc_caps.h"
 #include "hal/timer_ll.h"
 #include "hal/timer_types.h"
-#include "soc/timer_group_caps.h"

 /**
 * Context that should be maintained by both the driver and the HAL
--- a/components/hal/include/hal/timer_types.h
+++ b/components/hal/include/hal/timer_types.h
@@ -21,8 +21,8 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include <esp_bit_defs.h>
-#include "soc/timer_group_caps.h"
 #include "esp_attr.h"
+#include "soc/soc_caps.h"

 /**
 * @brief Selects a Timer-Group out of 2 available groups
--- a/components/hal/include/hal/touch_sensor_types.h
+++ b/components/hal/include/hal/touch_sensor_types.h
@@ -15,11 +15,10 @@
 #pragma once

 #include <stdbool.h>
-
-#include "soc/soc.h"
-#include "soc/touch_sensor_caps.h"
-#include "sdkconfig.h"
 #include "esp_attr.h"
+#include "soc/soc.h"
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"

 /** Touch pad channel */
 typedef enum {
@@ -115,9 +114,10 @@ typedef enum {
 } touch_trigger_src_t;

 /********************************/
+#define TOUCH_PAD_BIT_MASK_ALL              ((1<<SOC_TOUCH_SENSOR_NUM)-1)
 #define TOUCH_PAD_SLOPE_DEFAULT             (TOUCH_PAD_SLOPE_7)
 #define TOUCH_PAD_TIE_OPT_DEFAULT           (TOUCH_PAD_TIE_OPT_LOW)
-#define TOUCH_PAD_BIT_MASK_MAX              (SOC_TOUCH_SENSOR_BIT_MASK_MAX)
+#define TOUCH_PAD_BIT_MASK_MAX              (TOUCH_PAD_BIT_MASK_ALL)
 #define TOUCH_PAD_HIGH_VOLTAGE_THRESHOLD    (TOUCH_HVOLT_2V7)
 #define TOUCH_PAD_LOW_VOLTAGE_THRESHOLD     (TOUCH_LVOLT_0V5)
 #define TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD   (TOUCH_HVOLT_ATTEN_0V5)
--- a/components/hal/include/hal/twai_types.h
+++ b/components/hal/include/hal/twai_types.h
@@ -21,6 +21,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include "sdkconfig.h"
+#include "soc/soc_caps.h"

 /**
 * @brief   TWAI Constants
@@ -46,6 +47,10 @@ extern "C" {
 #define TWAI_MSG_FLAG_SELF              0x08        /**< Transmit as a Self Reception Request. Unused for received. */
 #define TWAI_MSG_FLAG_DLC_NON_COMP      0x10        /**< Message's Data length code is larger than 8. This will break compliance with TWAI */

+#define TWAI_BRP_MAX    SOC_TWAI_BRP_MAX    /**< Maximum configurable BRP value */
+#define TWAI_BRP_MIN    SOC_TWAI_BRP_MIN    /**< Minimum configurable BRP value */
+
+
 /**
 * @brief Initializer macros for timing configuration structure
 *
@@ -55,12 +60,12 @@ extern "C" {
 * @note These timing values are based on the assumption APB clock is at 80MHz
 * @note The available bit rates are dependent on the chip target and revision.
 */
-#if (TWAI_BRP_MAX > 256)
+#if (SOC_TWAI_BRP_MAX > 256)
 #define TWAI_TIMING_CONFIG_1KBITS()     {.brp = 4000, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_5KBITS()     {.brp = 800, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_10KBITS()    {.brp = 400, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #endif
-#if (TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
+#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
 #define TWAI_TIMING_CONFIG_12_5KBITS()  {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_16KBITS()    {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_20KBITS()    {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
--- a/components/hal/include/hal/uart_types.h
+++ b/components/hal/include/hal/uart_types.h
@@ -20,7 +20,7 @@ extern "C" {

 #include <stdint.h>
 #include <stdbool.h>
-#include "soc/uart_caps.h"
+#include "soc/soc_caps.h"


 /**
--- a/components/hal/include/hal/wdt_hal.h
+++ b/components/hal/include/hal/wdt_hal.h
@@ -25,7 +25,7 @@ extern "C" {
 #endif

 #include <stdbool.h>
-#include "soc/timer_group_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/wdt_types.h"
 #include "hal/mwdt_ll.h"
 #include "hal/rwdt_ll.h"
--- a/components/hal/mpu_hal.c
+++ b/components/hal/mpu_hal.c
@@ -21,7 +21,7 @@
 #include "hal/mpu_ll.h"
 #include "hal/mpu_types.h"

-#include "soc/mpu_caps.h"
+#include "soc/soc_caps.h"

 void mpu_hal_set_region_access(int id, mpu_access_t access)
 {
--- a/components/hal/spi_flash_hal.c
+++ b/components/hal/spi_flash_hal.c
@@ -15,7 +15,7 @@
 #include <stdlib.h>
 #include "hal/spi_flash_hal.h"
 #include "string.h"
-#include "soc/spi_caps.h"
+#include "soc/soc_caps.h"
 #include "hal/hal_defs.h"

 #define APB_CYCLE_NS   (1000*1000*1000LL/APB_CLK_FREQ)
--- a/components/hal/twai_hal.c
+++ b/components/hal/twai_hal.c
@@ -32,7 +32,7 @@ bool twai_hal_init(twai_hal_context_t *hal_ctx)
    if (!twai_ll_is_in_reset_mode(hal_ctx->dev)) {    //Must enter reset mode to write to config registers
        return false;
    }
-#ifdef TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT
+#ifdef SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT
    twai_ll_enable_extended_reg_layout(hal_ctx->dev);        //Changes the address layout of the registers
 #endif
    twai_ll_set_mode(hal_ctx->dev, TWAI_MODE_LISTEN_ONLY);    //Freeze REC by changing to LOM mode
@@ -70,7 +70,7 @@ void twai_hal_start(twai_hal_context_t *hal_ctx, twai_mode_t mode)
    twai_ll_set_mode(hal_ctx->dev, mode);                //Set operating mode
    (void) twai_ll_get_and_clear_intrs(hal_ctx->dev);    //Clear any latched interrupts
    TWAI_HAL_SET_FLAG(hal_ctx->state_flags, TWAI_HAL_STATE_FLAG_RUNNING);
-    twai_ll_exit_reset_mode(hal_ctx->dev); 
+    twai_ll_exit_reset_mode(hal_ctx->dev);
 }

 void twai_hal_stop(twai_hal_context_t *hal_ctx)