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soc: combine xxx_caps.h into one soc_caps.h

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During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
This commit is contained in:
Michael (XIAO Xufeng)
2020-09-10 10:37:58 +08:00
parent bd7fecd396
commit 647dea9395
182 changed files with 1047 additions and 1387 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
components/hal/esp32/adc_hal.c
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@@ -15,6 +15,7 @@
// The HAL layer for ADC (common part)
#include "hal/adc_hal.h"
#include "hal/adc_hal_conf.h"
#include "hal/adc_types.h"
void adc_hal_digi_init(void)

31
components/hal/esp32/include/hal/adc_hal_conf.h Normal file
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@@ -0,0 +1,31 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_ADC1_DATA_INVERT_DEFAULT (1)
#define SOC_ADC2_DATA_INVERT_DEFAULT (1)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
#define SOC_ADC_FSM_START_WAIT_DEFAULT (SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (16)

2
components/hal/esp32/include/hal/can_types.h
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@@ -38,7 +38,7 @@ extern "C" {
#define CAN_MSG_FLAG_SELF TWAI_MSG_FLAG_SELF
#define CAN_MSG_FLAG_DLC_NON_COMP TWAI_MSG_FLAG_DLC_NON_COMP
#if (TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
#define CAN_TIMING_CONFIG_12_5KBITS() TWAI_TIMING_CONFIG_12_5KBITS()
#define CAN_TIMING_CONFIG_16KBITS() TWAI_TIMING_CONFIG_16KBITS()
#define CAN_TIMING_CONFIG_20KBITS() TWAI_TIMING_CONFIG_20KBITS()

2
components/hal/esp32/include/hal/cpu_ll.h
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@@ -17,7 +17,7 @@
#include "esp_attr.h"
#include "soc/cpu_caps.h"
#include "soc/soc_caps.h"
#include "xt_instr_macros.h"
#include "xtensa/config/specreg.h"

10
components/hal/esp32/include/hal/gpio_ll.h
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@@ -35,6 +35,12 @@ extern "C" {
// Get GPIO hardware instance with giving gpio num
#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
#define GPIO_LL_APP_CPU_INTR_ENA (BIT(0))
#define GPIO_LL_APP_CPU_NMI_INTR_ENA (BIT(1))
#define GPIO_LL_PRO_CPU_INTR_ENA (BIT(2))
#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(3))
#define GPIO_LL_SDIO_EXT_INTR_ENA (BIT(4))
/**
* @brief Enable pull-up on GPIO.
*
@@ -147,9 +153,9 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
{
if (core_id == 0) {
hw->pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr
hw->pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr
} else {
hw->pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr
hw->pin[gpio_num].int_ena = GPIO_LL_APP_CPU_INTR_ENA; //enable pro cpu intr
}
}

12
components/hal/esp32/include/hal/i2c_ll.h
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@@ -22,6 +22,8 @@
extern "C" {
#endif
#define I2C_LL_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */
/**
* @brief I2C hardware cmd register filed.
*/
@@ -42,7 +44,7 @@ typedef union {
* @brief I2C interrupt event
*/
typedef enum {
I2C_INTR_EVENT_ERR,
I2C_INTR_EVENT_ERR,
I2C_INTR_EVENT_ARBIT_LOST, /*!< I2C arbition lost event */
I2C_INTR_EVENT_NACK, /*!< I2C NACK event */
I2C_INTR_EVENT_TOUT, /*!< I2C time out event */
@@ -329,7 +331,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;
hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;
}
/**
@@ -342,7 +344,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
*/
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.rx_fifo_full_thrhd = full_thr;
hw->fifo_conf.rx_fifo_full_thrhd = full_thr;
}
/**
@@ -533,7 +535,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
for(int i = 0; i < len; i++) {
WRITE_PERI_REG(fifo_addr, ptr[i]);
}
}
}
/**
@@ -549,7 +551,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
{
for(int i = 0; i < len; i++) {
ptr[i] = hw->fifo_data.data;
}
}
}
/**

2
components/hal/esp32/include/hal/mcpwm_ll.h
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@@ -22,10 +22,10 @@
#pragma once
#include "soc/soc_caps.h"
#include <soc/mcpwm_periph.h>
#include "soc/mcpwm_periph.h"
#include "hal/mcpwm_types.h"
#include "soc/mcpwm_caps.h"
#include "hal/hal_defs.h"
#include "esp_types.h"

2
components/hal/esp32/include/hal/mpu_ll.h
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@@ -14,7 +14,7 @@
#include <stdint.h>
#include "soc/mpu_caps.h"
#include "soc/soc_caps.h"
#include "xt_instr_macros.h"

2
components/hal/esp32/include/hal/rmt_ll.h
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@@ -19,7 +19,7 @@ extern "C" {
#include <stdbool.h>
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
#include "soc/soc_caps.h"
#define RMT_LL_HW_BASE (&RMT)
#define RMT_LL_MEM_BASE (&RMTMEM)

4
components/hal/esp32/include/hal/rtc_io_ll.h
View File

@@ -25,6 +25,8 @@
#include "hal/rtc_io_types.h"
#include "hal/gpio_types.h"
#define RTCIO_LL_PIN_FUNC 0
#ifdef __cplusplus
extern "C" {
#endif
@@ -58,7 +60,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
//0:RTC FUNCTION 1,2,3:Reserved
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[rtcio_num].func);
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
} else if (func == RTCIO_FUNC_DIGITAL) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
}

2
components/hal/esp32/include/hal/touch_sensor_ll.h
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@@ -62,7 +62,7 @@ static inline void touch_ll_set_meas_time(uint16_t meas_time)
//touch sensor measure time= meas_cycle / 8Mhz
SENS.sar_touch_ctrl1.touch_meas_delay = meas_time;
//the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
SENS.sar_touch_ctrl1.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT;
SENS.sar_touch_ctrl1.touch_xpd_wait = SOC_TOUCH_PAD_MEASURE_WAIT_MAX;
}
/**

6
components/hal/esp32/include/hal/twai_ll.h
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@@ -331,7 +331,7 @@ static inline uint32_t twai_ll_get_and_clear_intrs(twai_dev_t *hw)
*/
static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask)
{
#if (CONFIG_ESP32_REV_MIN >= 2)
#if TWAI_BRP_DIV_SUPPORTED
//ESP32 Rev 2 or later has brp div field. Need to mask it out
hw->interrupt_enable_reg.val = (hw->interrupt_enable_reg.val & 0x10) | intr_mask;
#else
@@ -357,8 +357,8 @@ static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask)
*/
static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling)
{
#if (CONFIG_ESP32_REV_MIN >= 2)
if (brp > TWAI_BRP_DIV_THRESH) {
#if TWAI_BRP_DIV_SUPPORTED
if (brp > SOC_TWAI_BRP_DIV_THRESH) {
//Need to set brp_div bit
hw->interrupt_enable_reg.brp_div = 1;
brp /= 2;

21
components/hal/esp32/include/hal/uart_ll.h
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@@ -17,21 +17,24 @@
#pragma once
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "hal/uart_types.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (UART_FIFO_LEN)
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (((num) == 1) ? (&UART1) : (&UART2)))
// The timeout calibration factor when using ref_tick
#define UART_LL_TOUT_REF_FACTOR_DEFAULT (8)
#define UART_LL_MIN_WAKEUP_THRESH (2)
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1<<0),
@@ -250,8 +253,8 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
uint32_t fifo_cnt = hw->status.rxfifo_cnt;
typeof(hw->mem_rx_status) rx_status = hw->mem_rx_status;
uint32_t len = 0;
// When using DPort to read fifo, fifo_cnt is not credible, we need to calculate the real cnt based on the fifo read and write pointer.
// When using DPort to read fifo, fifo_cnt is not credible, we need to calculate the real cnt based on the fifo read and write pointer.
// When using AHB to read FIFO, we can use fifo_cnt to indicate the data length in fifo.
if (rx_status.wr_addr > rx_status.rd_addr) {
len = rx_status.wr_addr - rx_status.rd_addr;
@@ -286,12 +289,12 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
*/
static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
{
//workaround for hardware issue, when UART stop bit set as 2-bit mode.
//workaround for hardware issue, when UART stop bit set as 2-bit mode.
if(stop_bit == UART_STOP_BITS_2) {
hw->rs485_conf.dl1_en = 1;
hw->conf0.stop_bit_num = 0x1;
} else {
hw->rs485_conf.dl1_en = 0;
hw->rs485_conf.dl1_en = 0;
hw->conf0.stop_bit_num = stop_bit;
}
}
@@ -306,7 +309,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
*/
static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
{
//workaround for hardware issue, when UART stop bit set as 2-bit mode.
//workaround for hardware issue, when UART stop bit set as 2-bit mode.
if(hw->rs485_conf.dl1_en == 1 && hw->conf0.stop_bit_num == 0x1) {
*stop_bit = UART_STOP_BITS_2;
} else {
@@ -573,7 +576,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
*/
static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
{
hw->sleep_conf.active_threshold = wakeup_thrd - SOC_UART_MIN_WAKEUP_THRESH;
hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
}
/**
@@ -715,7 +718,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
*/
static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
{
return hw->sleep_conf.active_threshold + SOC_UART_MIN_WAKEUP_THRESH;
return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
}
/**

4
components/hal/esp32/touch_sensor_hal.c
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@@ -20,8 +20,8 @@
void touch_hal_init(void)
{
touch_ll_intr_disable();
touch_ll_clear_channel_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX);
touch_ll_clear_group_mask(SOC_TOUCH_SENSOR_BIT_MASK_MAX, SOC_TOUCH_SENSOR_BIT_MASK_MAX);
touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
touch_ll_clear_group_mask(TOUCH_PAD_BIT_MASK_ALL, TOUCH_PAD_BIT_MASK_ALL);
touch_ll_set_trigger_mode(TOUCH_TRIGGER_MODE_DEFAULT);
touch_ll_set_trigger_source(TOUCH_TRIGGER_SOURCE_DEFAULT);
touch_ll_clear_trigger_status_mask();