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soc: combine xxx_caps.h into one soc_caps.h

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During HAL layer refactoring and new chip bringup, we have several
caps.h for each part, to reduce the conflicts to minimum. But this is
The capabilities headers will be relataive stable once completely
written (maybe after the featues are supported by drivers).

Now ESP32 and ESP32-S2 drivers are relative stable, making it a good
time to combine all these caps.h into one soc_caps.h

This cleanup also move HAL config and pin config into separated files,
to make the responsibilities of these headers more clear. This is
helpful for the stabilities of soc_caps.h because we want to make it
public some day.
This commit is contained in:
Michael (XIAO Xufeng)
2020-09-10 10:37:58 +08:00
parent bd7fecd396
commit 647dea9395
182 changed files with 1047 additions and 1387 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/soc/soc/esp32/gpio_periph.c
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@@ -14,7 +14,7 @@
#include "soc/gpio_periph.h"
const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO0_REG,
IO_MUX_GPIO1_REG,
IO_MUX_GPIO2_REG,
@@ -57,7 +57,7 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
IO_MUX_GPIO39_REG,
};
const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = {
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
0,
BIT(1),
0,

31
components/soc/soc/esp32/include/soc/adc_caps.h
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@@ -1,31 +0,0 @@
#pragma once
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
#define SOC_ADC1_DATA_INVERT_DEFAULT (1)
#define SOC_ADC2_DATA_INVERT_DEFAULT (1)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
#define SOC_ADC_FSM_START_WAIT_DEFAULT (SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT * 2)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2)
/**
* Check if adc support digital controller (DMA) mode.
* @value
* - 1 : support;
* - 0 : not support;
*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 0)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (2)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (16)

33
components/soc/soc/esp32/include/soc/can_caps.h
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@@ -1,33 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#warning soc/can_caps.h is deprecated, please use soc/twai_caps.h instead
/* ---------------------------- Compatibility ------------------------------- */
#define CAN_BRP_MIN 2
#define CAN_BRP_MAX 128
#define CAN_BRP_MAX_ECO 256
#define CAN_BRP_DIV_THRESH 128
#define CAN_SUPPORT_MULTI_ADDRESS_LAYOUT 1
#ifdef __cplusplus
}
#endif

2
components/soc/soc/esp32/include/soc/can_periph.h
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@@ -23,8 +23,8 @@ extern "C" {
#warning soc/can_periph.h is deprecated, please use soc/twai_periph.h instead
#if CONFIG_IDF_TARGET_ESP32
#include "soc/soc_caps.h"
#include "soc/can_struct.h"
#include "soc/can_caps.h"
#endif
#ifdef __cplusplus

20
components/soc/soc/esp32/include/soc/cpu_caps.h
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@@ -1,20 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes

22
components/soc/soc/esp32/include/soc/dac_caps.h
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@@ -1,22 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_DAC_CAPS_H_
#define _SOC_RTC_DAC_CAPS_H_
#define SOC_DAC_PERIPH_NUM 2
#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
#endif

51
components/soc/soc/esp32/include/soc/gpio_caps.h
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@@ -1,51 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define GPIO_PIN_COUNT (40)
// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (0)
// Force hold is a new function of ESP32-S2
#define GPIO_SUPPORTS_FORCE_HOLD (0)
#define GPIO_APP_CPU_INTR_ENA (BIT(0))
#define GPIO_APP_CPU_NMI_INTR_ENA (BIT(1))
#define GPIO_PRO_CPU_INTR_ENA (BIT(2))
#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(3))
#define GPIO_SDIO_EXT_INTR_ENA (BIT(4))
#define GPIO_MODE_DEF_DISABLE (0)
#define GPIO_MODE_DEF_INPUT (BIT0)
#define GPIO_MODE_DEF_OUTPUT (BIT1)
#define GPIO_MODE_DEF_OD (BIT2)
#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) /*!< Check whether it can be a valid GPIO number of output mode */
#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) /*!< Check whether it contains input io */
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
#ifdef __cplusplus
}
#endif

5
components/soc/soc/esp32s2/include/soc/ledc_caps.h → components/soc/soc/esp32/include/soc/gpio_pins.h
View File

@@ -3,6 +3,7 @@
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@@ -17,7 +18,9 @@
extern "C" {
#endif
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
#ifdef __cplusplus
}

36
components/soc/soc/esp32/include/soc/i2c_caps.h
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@@ -1,36 +0,0 @@
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32 have 2 I2C.
#define SOC_I2C_NUM (2)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define I2C_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */
//ESP32 do not support hardware FSM reset
#define I2C_SUPPORT_HW_FSM_RST (0)
//ESP32 do not support hardware clear bus
#define I2C_SUPPORT_HW_CLR_BUS (0)
#ifdef __cplusplus
}
#endif

37
components/soc/soc/esp32/include/soc/i2s_caps.h
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@@ -1,37 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define APLL_MIN_FREQ (250000000)
#define APLL_MAX_FREQ (500000000)
#define APLL_I2S_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define I2S_AD_BCK_FACTOR (2)
#define I2S_PDM_BCK_FACTOR (64)
#define I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define I2S_BASE_CLK (2*APB_CLK_FREQ)
// ESP32 have 2 I2S
#define SOC_I2S_NUM (2)
#define SOC_I2S_SUPPORTS_PDM (1) // ESP32 support PDM
#define SOC_I2S_SUPPORTS_DMA_EQUAL (0) // ESP32 don't support dma equal
#define SOC_I2S_SUPPORTS_ADC_DAC (1) // ESP32 support ADC and DAC
#ifdef __cplusplus
}
#endif

22
components/soc/soc/esp32/include/soc/mcpwm_caps.h
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@@ -1,22 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_MCPWM_PERIPH_NUM 2 ///< MCPWM peripheral number
#define SOC_MCPWM_TIMER_NUM 3 ///< Timer that each peripheral has
#define SOC_MCPWM_OP_NUM 3 ///< Operator that each peripheral has
#define SOC_MCPWM_COMPARATOR_NUM 2 ///< Comparator that each operator has
#define SOC_MCPWM_GENERATOR_NUM 2 ///< Generator that each operator has
#define SOC_MCPWM_FAULT_SIG_NUM 3 ///< Fault signal number that each peripheral has

21
components/soc/soc/esp32/include/soc/mpu_caps.h
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@@ -1,21 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
#define SOC_MPU_MIN_REGION_SIZE 0x20000000
#define SOC_MPU_REGIONS_MAX_NUM 8
#define SOC_MPU_REGION_RO_SUPPORTED 0
#define SOC_MPU_REGION_WO_SUPPORTED 0

26
components/soc/soc/esp32/include/soc/rmt_caps.h
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@@ -1,26 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels */
#ifdef __cplusplus
}
#endif

21
components/soc/soc/esp32/include/soc/rtc_io_caps.h
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@@ -1,21 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_IO_CAPS_H_
#define _SOC_RTC_IO_CAPS_H_
#define SOC_RTC_IO_PIN_COUNT 18
#define SOC_PIN_FUNC_RTC_IO 0
#endif

37
components/soc/soc/esp32/include/soc/sigmadelta_caps.h
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@@ -1,37 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32 have 1 SIGMADELTA peripheral.
#define SIGMADELTA_PORT_0 (0) /*!< SIGMADELTA port 0 */
#define SIGMADELTA_PORT_MAX (1) /*!< SIGMADELTA port max */
#define SOC_SIGMADELTA_NUM (SIGMADELTA_PORT_MAX)
#define SIGMADELTA_CHANNEL_0 (0) /*!< Sigma-delta channel 0 */
#define SIGMADELTA_CHANNEL_1 (1) /*!< Sigma-delta channel 1 */
#define SIGMADELTA_CHANNEL_2 (2) /*!< Sigma-delta channel 2 */
#define SIGMADELTA_CHANNEL_3 (3) /*!< Sigma-delta channel 3 */
#define SIGMADELTA_CHANNEL_4 (4) /*!< Sigma-delta channel 4 */
#define SIGMADELTA_CHANNEL_5 (5) /*!< Sigma-delta channel 5 */
#define SIGMADELTA_CHANNEL_6 (6) /*!< Sigma-delta channel 6 */
#define SIGMADELTA_CHANNEL_7 (7) /*!< Sigma-delta channel 7 */
#define SIGMADELTA_CHANNEL_MAX (8)
#ifdef __cplusplus
}
#endif

245
components/soc/soc/esp32/include/soc/soc_caps.h
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@@ -1,16 +1,237 @@
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* Soc capabilities file, describing the following chip attributes:
* - Peripheral or feature supported or not
* - Number of resources (peripheral, channel, etc.)
* - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency
* supported, etc.
*
* For boolean definitions:
* - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`.
* (`#define` blank string causes error when checking by `#if x`)
* - if false: not define anything at all.
* (`#ifdef x` is true even when `#define 0` is defined before.)
*
* The code depending on this file uses these boolean definitions as `#if x` or `#if !x`.
* (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define
* x 0`, it's still a risk.)
*
* ECO & exceptions:
* For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by
* `#if x` and `#if !x`, making these missing definitions more obvious.
*/
#pragma once
#define SOC_MCPWM_SUPPORTED 1
#define SOC_SDMMC_HOST_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#ifdef __has_include
# if __has_include("sdkconfig.h")
# include "sdkconfig.h"
# define SOC_CAPS_ECO_VER CONFIG_ESP32_REV_MIN
# endif
#endif
#if __DOXYGEN__ && !defined(SOC_CAPS_ECO_VER)
#define SOC_CAPS_ECO_VER SOC_CAPS_ECO_VER_MAX
#endif
#ifndef SOC_CAPS_ECO_VER
#warning ECO version not determined. Some ECO related caps will not be available.
#warning Define SOC_CAPS_ECO_VER before including this header.
// Define warning strings here for ECO-ed features to show error when they are used without being
// defined correctly
#define SOC_BROWNOUT_RESET_SUPPORTED "Not determined"
#define SOC_TWAI_BRP_DIV_SUPPORTED "Not determined"
#endif
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_CAPS_ECO_VER_MAX 3
#define SOC_MCPWM_SUPPORTED 1
#define SOC_SDMMC_HOST_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#define SOC_SDIO_SLAVE_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_CAN_SUPPORTED SOC_TWAI_SUPPORTED
#define SOC_EMAC_SUPPORTED 1
#define SOC_RISCV_COPROC_SUPPORTED 0
#define SOC_CPU_CORES_NUM 2
#define SOC_TWAI_SUPPORTED 1
#define SOC_EMAC_SUPPORTED 1
#define SOC_RISCV_COPROC_SUPPORTED 0 //TODO: correct the caller and remove this line
#define SOC_CPU_CORES_NUM 2
/*-------------------------- ADC CAPS ----------------------------------------*/
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
/**
* Check if adc support digital controller (DMA) mode.
* @value
* - 1 : support;
* - 0 : not support;
*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 0)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#if SOC_CAPS_ECO_VER >= 1
#define SOC_BROWNOUT_RESET_SUPPORTED 1
#endif
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
/*-------------------------- DAC CAPS ----------------------------------------*/
#define SOC_DAC_PERIPH_NUM 2
#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT 40
// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (0)
// Force hold is a new function of ESP32-S2
#define SOC_GPIO_SUPPORT_FORCE_HOLD (0)
// 0~39 except from 20, 24, 28~31 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT20 | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
// GPIO >= 34 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32 have 2 I2C.
#define SOC_I2C_NUM (2)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
//ESP32 do not support hardware FSM reset
#define SOC_I2C_SUPPORT_HW_FSM_RST (0)
//ESP32 do not support hardware clear bus
#define SOC_I2C_SUPPORT_HW_CLR_BUS (0)
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32 have 2 I2S
#define SOC_I2S_NUM (2)
#define SOC_I2S_SUPPORTS_PDM (1) // ESP32 support PDM
#define SOC_I2S_SUPPORTS_DMA_EQUAL (0) // ESP32 don't support dma equal
#define SOC_I2S_SUPPORTS_ADC_DAC (1) // ESP32 support ADC and DAC
#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_HS_MODE (1)
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_PERIPH_NUM 2 ///< MCPWM peripheral number
#define SOC_MCPWM_TIMER_NUM 3 ///< Timer that each peripheral has
#define SOC_MCPWM_OP_NUM 3 ///< Operator that each peripheral has
#define SOC_MCPWM_COMPARATOR_NUM 2 ///< Comparator that each operator has
#define SOC_MCPWM_GENERATOR_NUM 2 ///< Generator that each operator has
#define SOC_MCPWM_FAULT_SIG_NUM 3 ///< Fault signal number that each peripheral has
/*-------------------------- MPU CAPS ----------------------------------------*/
//TODO: correct the caller and remove unsupported lines
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
#define SOC_MPU_MIN_REGION_SIZE 0x20000000
#define SOC_MPU_REGIONS_MAX_NUM 8
#define SOC_MPU_REGION_RO_SUPPORTED 0
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
// ESP32 have 1 PCNT peripheral
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (8)
/*-------------------------- RMT CAPS ----------------------------------------*/
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory */
#define SOC_RMT_CHANNELS_NUM (8) /*!< Total 8 channels */
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 18
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
// ESP32 have 1 SIGMADELTA peripheral.
#define SOC_SIGMADELTA_NUM 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_DMA_CHAN_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 3
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_AS_CS 1 //Support to toggle the CS while the clock toggles
// Peripheral supports DIO, DOUT, QIO, or QOUT
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;})
// Peripheral doesn't support output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_host) ({(void)spi_host; 0;})
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
// No contents here
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (10)
#define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */
#define SOC_TOUCH_PAD_THRESHOLD_MAX (0) /*!<If set touch threshold max value, The touch sensor can't be in touched status */
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_BRP_MIN 2
#define SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 1
#define SOC_TWAI_BRP_MAX_ECO0 128
//Any even number from 2 to 128
#define SOC_TWAI_BRP_IS_VALID_ECO0(brp) ((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0)
#define SOC_TWAI_BRP_MAX_ECO 256
//Any even number from 2 to 128, or multiples of 4 from 132 to 256
#define SOC_TWAI_BRP_IS_VALID_ECO(brp) (((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0) || ((brp) >= 132 && (brp) <= 256 && ((brp) & 0x3) == 0))
#if SOC_CAPS_ECO_VER >= 2
# define SOC_TWAI_BRP_DIV_SUPPORTED 1
# define SOC_TWAI_BRP_DIV_THRESH 128
# define SOC_TWAI_BRP_IS_VALID SOC_TWAI_BRP_IS_VALID_ECO
# define SOC_TWAI_BRP_MAX SOC_TWAI_BRP_MAX_ECO
#else
# define SOC_TWAI_BRP_IS_VALID SOC_TWAI_BRP_IS_VALID_ECO0
# define SOC_TWAI_BRP_MAX SOC_TWAI_BRP_MAX_ECO0
#endif
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32 have 3 UART.
#define SOC_UART_NUM (3)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
/* ---------------------------- Compatibility ------------------------------- */
#define SOC_CAN_SUPPORTED SOC_TWAI_SUPPORTED
#define CAN_BRP_MIN SOC_TWAI_BRP_MIN
#define CAN_BRP_MAX SOC_TWAI_BRP_MAX
#define CAN_BRP_DIV_THRESH SOC_TWAI_BRP_DIV_THRESH
#define CAN_SUPPORT_MULTI_ADDRESS_LAYOUT SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT

14
components/soc/soc/esp32s2/include/soc/cpu_caps.h → components/soc/soc/esp32/include/soc/soc_pins.h
View File

@@ -12,9 +12,15 @@
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* Pin definition header file. The long term plan is to have a single soc_pins.h for all
* peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
* peripheral and include them here to avoid developing conflicts in those header files.
*/
#pragma once
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
#include "soc/sdio_slave_pins.h"
#include "soc/sdmmc_pins.h"

17
components/soc/soc/esp32/include/soc/spi_caps.h → components/soc/soc/esp32/include/soc/spi_pins.h
View File

@@ -14,10 +14,6 @@
#pragma once
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_DMA_CHAN_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 3
#define SPI_FUNC_NUM 1
#define SPI_IOMUX_PIN_NUM_MISO 7
#define SPI_IOMUX_PIN_NUM_MOSI 8
@@ -51,17 +47,4 @@
#define VSPI_IOMUX_PIN_NUM_WP 22
#define VSPI_IOMUX_PIN_NUM_HD 21
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_AS_CS 1 //Support to toggle the CS while the clock toggles
//#define SOC_SPI_SUPPORT_DDRCLK
//#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
//#define SOC_SPI_SUPPORT_CD_SIG
// Peripheral supports DIO, DOUT, QIO, or QOUT
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;})
// Peripheral doesn't support output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_host) ({(void)spi_host; 0;})

15
components/soc/soc/esp32/include/soc/timer_group_caps.h
View File

@@ -1,15 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once

29
components/soc/soc/esp32/include/soc/touch_sensor_caps.h
View File

@@ -1,29 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_TOUCH_SENSOR_NUM (10)
#define SOC_TOUCH_SENSOR_BIT_MASK_MAX (0x3ff)
#define SOC_TOUCH_PAD_MEASURE_WAIT (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */
#define SOC_TOUCH_PAD_THRESHOLD_MAX (0) /*!<If set touch threshold max value, The touch sensor can't be in touched status */
#ifdef __cplusplus
}
#endif

29
components/soc/soc/esp32/include/soc/twai_caps.h
View File

@@ -1,29 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define TWAI_BRP_MIN 2
#define TWAI_BRP_MAX 128
#define TWAI_BRP_MAX_ECO 256
#define TWAI_BRP_DIV_THRESH 128
#define TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 1
#ifdef __cplusplus
}
#endif

33
components/soc/soc/esp32/include/soc/uart_caps.h
View File

@@ -1,33 +0,0 @@
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
// ESP32 have 3 UART.
#define SOC_UART_NUM (3)
#define SOC_UART_MIN_WAKEUP_THRESH (2)
#define UART_INTR_MASK (0x7ffff) //All interrupt mask
#ifdef __cplusplus
}
#endif

4
components/soc/soc/esp32/rtc_io_periph.c
View File

@@ -14,7 +14,7 @@
#include "soc/rtc_io_periph.h"
const int rtc_io_num_map[GPIO_PIN_COUNT] = {
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0
-1,//GPIO1
RTCIO_GPIO2_CHANNEL, //GPIO2
@@ -58,7 +58,7 @@ const int rtc_io_num_map[GPIO_PIN_COUNT] = {
};
//Reg,Mux,Fun,IE,Up,Down,Rtc_number
const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT] = {
const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = {
/*REG MUX select function select Input enable Pullup Pulldown Sleep select Sleep input enable PAD hold Pad force hold Mask of drive capability Offset gpio number */
{RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, RTC_IO_SENSE1_SLP_SEL_M, RTC_IO_SENSE1_SLP_IE_M, 0, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE1_HOLD_FORCE_M, 0, 0, RTCIO_CHANNEL_0_GPIO_NUM}, //36
{RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, 0, RTC_IO_SENSE2_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, RTCIO_CHANNEL_1_GPIO_NUM}, //37

4
components/soc/soc/esp32s2/gpio_periph.c
View File

@@ -14,7 +14,7 @@
#include "soc/gpio_periph.h"
const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO0_REG,
IO_MUX_GPIO1_REG,
IO_MUX_GPIO2_REG,
@@ -65,7 +65,7 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
0,
};
const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = {
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
0,
0,
0,

31
components/soc/soc/esp32s2/include/soc/adc_caps.h
View File

@@ -1,31 +0,0 @@
#pragma once
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
#define SOC_ADC1_DATA_INVERT_DEFAULT (0)
#define SOC_ADC2_DATA_INVERT_DEFAULT (0)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (3)
/**
* Check if adc support digital controller (DMA) mode.
* @value
* - 1 : support;
* - 0 : not support;
*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (2)

22
components/soc/soc/esp32s2/include/soc/dac_caps.h
View File

@@ -1,22 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_DAC_CAPS_H_
#define _SOC_RTC_DAC_CAPS_H_
#define SOC_DAC_PERIPH_NUM 2
#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
#endif

48
components/soc/soc/esp32s2/include/soc/gpio_caps.h
View File

@@ -1,48 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S2 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define GPIO_PIN_COUNT (48)
// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S2
#define GPIO_SUPPORTS_FORCE_HOLD (1)
#define GPIO_PRO_CPU_INTR_ENA (BIT(0))
#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(1))
#define GPIO_MODE_DEF_DISABLE (0)
#define GPIO_MODE_DEF_INPUT (BIT0)
#define GPIO_MODE_DEF_OUTPUT (BIT1)
#define GPIO_MODE_DEF_OD (BIT2)
#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */
#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_46))) /*!< Check whether it contains input io */
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif

4
components/soc/soc/esp32/include/soc/ledc_caps.h → components/soc/soc/esp32s2/include/soc/gpio_pins.h
View File

@@ -3,6 +3,7 @@
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@@ -17,7 +18,8 @@
extern "C" {
#endif
#define SOC_LEDC_SUPPORT_HS_MODE (1)
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}

36
components/soc/soc/esp32s2/include/soc/i2c_caps.h
View File

@@ -1,36 +0,0 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S2 have 2 I2C.
#define SOC_I2C_NUM (2)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define I2C_INTR_MASK (0x1ffff) /*!< I2C all interrupt bitmap */
//ESP32-S2 support hardware FSM reset
#define I2C_SUPPORT_HW_FSM_RST (1)
//ESP32-S2 support hardware clear bus
#define I2C_SUPPORT_HW_CLR_BUS (1)
#ifdef __cplusplus
}
#endif

30
components/soc/soc/esp32s2/include/soc/i2s_caps.h
View File

@@ -1,30 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define APLL_MIN_FREQ (250000000)
#define APLL_MAX_FREQ (500000000)
#define APLL_I2S_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define I2S_AD_BCK_FACTOR (2)
#define I2S_PDM_BCK_FACTOR (64)
#define I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define I2S_BASE_CLK (2*APB_CLK_FREQ)
// ESP32-S2 have 2 I2S
#define SOC_I2S_NUM (1)
#define SOC_I2S_SUPPORTS_PDM (0) // ESP32-S2 don't support PDM
#define SOC_I2S_SUPPORTS_DMA_EQUAL (1) // ESP32-S2 need dma equal
#define SOC_I2S_SUPPORTS_ADC_DAC (0) // ESP32-S2 don't support ADC and DAC

21
components/soc/soc/esp32s2/include/soc/mpu_caps.h
View File

@@ -1,21 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
#define SOC_MPU_MIN_REGION_SIZE 0x20000000
#define SOC_MPU_REGIONS_MAX_NUM 8
#define SOC_MPU_REGION_RO_SUPPORTED 0
#define SOC_MPU_REGION_WO_SUPPORTED 0

27
components/soc/soc/esp32s2/include/soc/pcnt_caps.h
View File

@@ -1,27 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S2 have 1 PCNT peripheral
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (4) // ESP32-S2 only have 4 unit
#ifdef __cplusplus
}
#endif

30
components/soc/soc/esp32s2/include/soc/rmt_caps.h
View File

@@ -1,30 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */
#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
#ifdef __cplusplus
}
#endif

18
components/soc/soc/esp32s2/include/soc/rtc_io_caps.h
View File

@@ -1,18 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_RTC_IO_PIN_COUNT 22
#define SOC_PIN_FUNC_RTC_IO 0

37
components/soc/soc/esp32s2/include/soc/sigmadelta_caps.h
View File

@@ -1,37 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S2 have 1 SIGMADELTA peripheral.
#define SIGMADELTA_PORT_0 (0) /*!< SIGMADELTA port 0 */
#define SIGMADELTA_PORT_MAX (1) /*!< SIGMADELTA port max */
#define SOC_SIGMADELTA_NUM (SIGMADELTA_PORT_MAX)
#define SIGMADELTA_CHANNEL_0 (0) /*!< Sigma-delta channel 0 */
#define SIGMADELTA_CHANNEL_1 (1) /*!< Sigma-delta channel 1 */
#define SIGMADELTA_CHANNEL_2 (2) /*!< Sigma-delta channel 2 */
#define SIGMADELTA_CHANNEL_3 (3) /*!< Sigma-delta channel 3 */
#define SIGMADELTA_CHANNEL_4 (4) /*!< Sigma-delta channel 4 */
#define SIGMADELTA_CHANNEL_5 (5) /*!< Sigma-delta channel 5 */
#define SIGMADELTA_CHANNEL_6 (6) /*!< Sigma-delta channel 6 */
#define SIGMADELTA_CHANNEL_7 (7) /*!< Sigma-delta channel 7 */
#define SIGMADELTA_CHANNEL_MAX (8)
#ifdef __cplusplus
}
#endif

205
components/soc/soc/esp32s2/include/soc/soc_caps.h
View File

@@ -1,10 +1,42 @@
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* Soc capabilities file, describing the following chip attributes:
* - Peripheral or feature supported or not
* - Number of resources (peripheral, channel, etc.)
* - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency
* supported, etc.
*
* For boolean definitions:
* - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`.
* (`#define` blank string causes error when checking by `#if x`)
* - if false: not define anything at all.
* (`#ifdef x` is true even when `#define 0` is defined before.)
*
* The code depending on this file uses these boolean definitions as `#if x` or `#if !x`.
* (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define
* x 0`, it's still a risk.)
*
* ECO & exceptions:
* For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by
* `#if x` and `#if !x`, making these missing definitions more obvious.
*/
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_TWAI_SUPPORTED 1
#define SOC_CP_DMA_SUPPORTED 1
#define SOC_CPU_CORES_NUM 1
@@ -12,4 +44,167 @@
#define SOC_RISCV_COPROC_SUPPORTED 1
#define SOC_USB_SUPPORTED 1
#define SOC_CACHE_SUPPORT_WRAP 1
#define SOC_CACHE_SUPPORT_WRAP 1
/*-------------------------- ADC CAPS ----------------------------------------*/
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
/**
* Check if adc support digital controller (DMA) mode.
* @value
* - 1 : support;
* - 0 : not support;
*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CP-DMA CAPS -------------------------------------*/
#define SOC_CP_DMA_MAX_BUFFER_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_BREAKPOINTS_NUM 2
#define SOC_CPU_WATCHPOINTS_NUM 2
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
/*-------------------------- DAC CAPS ----------------------------------------*/
#define SOC_DAC_PERIPH_NUM 2
#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-S2 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (48)
// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S2
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// 0~47 except from 22~25, 47 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47))
// GPIO 46, 47 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47))
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-S2 have 2 I2C.
#define SOC_I2C_NUM (2)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
//ESP32-S2 support hardware FSM reset
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
//ESP32-S2 support hardware clear bus
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32-S2 have 2 I2S
#define SOC_I2S_NUM (1)
#define SOC_I2S_SUPPORTS_PDM (0) // ESP32-S2 don't support PDM
#define SOC_I2S_SUPPORTS_DMA_EQUAL (1) // ESP32-S2 need dma equal
#define SOC_I2S_SUPPORTS_ADC_DAC (0) // ESP32-S2 don't support ADC and DAC
#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
/*-------------------------- MPU CAPS ----------------------------------------*/
//TODO: correct the caller and remove unsupported lines
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
#define SOC_MPU_MIN_REGION_SIZE 0x20000000
#define SOC_MPU_REGIONS_MAX_NUM 8
#define SOC_MPU_REGION_RO_SUPPORTED 0
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
// ESP32-S2 have 1 PCNT peripheral
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (4) // ESP32-S2 only have 4 unit
/*-------------------------- RMT CAPS ----------------------------------------*/
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */
#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 22
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
// ESP32-S2 have 1 SIGMADELTA peripheral.
#define SOC_SIGMADELTA_NUM 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_DMA_CHAN_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72
//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
/// The SPI Slave half duplex mode has been updated greatly in ESP32-S2
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// VSPI (SPI3) only support 1-bit mode
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2)
// Peripheral supports output given level during its "dummy phase"
// Only SPI1 supports this feature
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id) ((host_id) == 0)
#define SOC_MEMSPI_IS_INDEPENDENT 1
/*-------------------------- SYS TIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
#define SOC_TIMER_GROUP_SUPPORT_XTAL
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (15) /*! 15 Touch channels */
#define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) /* Sopport touch proximity channel number. */
#define SOC_TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF) /*!<If set touch threshold max value, The touch sensor can't be in touched status */
#define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_BRP_MIN 2
#define SOC_TWAI_BRP_MAX 32768
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-S2 have 2 UART.
#define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_PERIPH_NUM 1
/* ---------------------------- Compatibility ------------------------------- */
// No contents

23
components/soc/soc/esp32/include/soc/brownout_caps.h → components/soc/soc/esp32s2/include/soc/soc_pins.h
View File

@@ -12,18 +12,15 @@
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* Pin definition header file. The long term plan is to have a single soc_pins.h for all
* peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
* peripheral and include them here to avoid developing conflicts in those header files.
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "sdkconfig.h"
#if __DOXYGEN__ || (CONFIG_ESP32_REV_MIN >= 1)
#define SOC_BROWNOUT_RESET_SUPPORTED 1
#endif
#ifdef __cplusplus
}
#endif
#include "soc/usb_pins.h"
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
#include "soc/touch_sensor_pins.h"

59
components/soc/soc/esp32s2/include/soc/spi_caps.h
View File

@@ -1,59 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_DMA_CHAN_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_HD 27
#define SPI_IOMUX_PIN_NUM_CS 29
#define SPI_IOMUX_PIN_NUM_MOSI 32
#define SPI_IOMUX_PIN_NUM_CLK 30
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
//TODO: add the next slot
#define FSPI_FUNC_NUM 4
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
//TODO: add the next slot
//HSPI has no iomux pins
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72
//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
/// The SPI Slave half duplex mode has been updated greatly in ESP32-S2
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// VSPI (SPI3) only support 1-bit mode
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2)
// Peripheral supports output given level during its "dummy phase"
// Only SPI1 supports this feature
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id) ((host_id) == 0)
#define SOC_MEMSPI_IS_INDEPENDENT 1

19
components/soc/soc/esp32s2/include/soc/spi_pins.h
View File

@@ -1,9 +1,9 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@@ -12,29 +12,22 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_PINS_H_
#define _SOC_SPI_PINS_H_
#pragma once
#define SPI_PERIPH_NUM 3
#define SPI_FUNC_NUM 2
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_HD 27
#define SPI_IOMUX_PIN_NUM_CS 29
#define SPI_IOMUX_PIN_NUM_MOSI 32
#define SPI_IOMUX_PIN_NUM_CLK 30
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
//TODO: add the next slot
#define FSPI_FUNC_NUM 0
#define FSPI_FUNC_NUM 4
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
//TODO: add the next slot
//HSPI and VSPI have no iomux pins
#endif
//SPI3 has no iomux pins

21
components/soc/soc/esp32s2/include/soc/systimer_caps.h
View File

@@ -1,21 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units
#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
#define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part

17
components/soc/soc/esp32s2/include/soc/timer_group_caps.h
View File

@@ -1,17 +0,0 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_TIMER_GROUP_SUPPORT_XTAL

11
components/soc/soc/esp32s2/include/soc/touch_sensor_caps.h → components/soc/soc/esp32s2/include/soc/touch_sensor_pins.h
View File

@@ -18,17 +18,10 @@
extern "C" {
#endif
#define SOC_TOUCH_SENSOR_NUM (15) /*! 15 Touch channels */
#define SOC_TOUCH_SENSOR_BIT_MASK_MAX (0x7fff)/*! 15 Touch channels */
#define SOC_TOUCH_PAD_MEASURE_WAIT (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */
#define SOC_TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF) /*!<If set touch threshold max value, The touch sensor can't be in touched status */
#define SOC_TOUCH_SHIELD_CHANNEL (14) /*!< The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) */
#define SOC_TOUCH_DENOISE_CHANNEL (0) /*!< T0 is an internal channel that does not have a corresponding external GPIO.
T0 will work simultaneously with the measured channel Tn. Finally, the actual
#define SOC_TOUCH_DENOISE_CHANNEL (0) /*!< T0 is an internal channel that does not have a corresponding external GPIO.
T0 will work simultaneously with the measured channel Tn. Finally, the actual
measured value of Tn is the value after subtracting lower bits of T0. */
#define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) /* Sopport touch proximity channel number. */
#ifdef __cplusplus
}

26
components/soc/soc/esp32s2/include/soc/twai_caps.h
View File

@@ -1,26 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define TWAI_BRP_MIN 2
#define TWAI_BRP_MAX 32768
#ifdef __cplusplus
}
#endif

32
components/soc/soc/esp32s2/include/soc/uart_caps.h
View File

@@ -1,32 +0,0 @@
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
// ESP32-S2 have 2 UART.
#define SOC_UART_NUM (2)
#define SOC_UART_MIN_WAKEUP_THRESH (2)
#define UART_INTR_MASK (0x7ffff) //All interrupt mask
#ifdef __cplusplus
}
#endif

17
components/soc/soc/esp32s2/include/soc/usb_caps.h
View File

@@ -1,17 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_USB_PERIPH_NUM 1

2
components/soc/soc/esp32s2/include/soc/usb_periph.h
View File

@@ -16,7 +16,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "soc/usb_pins.h"
#include "soc/soc_pins.h"
#include "soc/gpio_sig_map.h"
#include "soc/usb_reg.h"
#include "soc/usb_types.h"

4
components/soc/soc/esp32s2/rtc_io_periph.c
View File

@@ -14,7 +14,7 @@
#include "soc/rtc_io_periph.h"
const int rtc_io_num_map[GPIO_PIN_COUNT] = {
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0
RTCIO_GPIO1_CHANNEL, //GPIO1
RTCIO_GPIO2_CHANNEL, //GPIO2
@@ -66,7 +66,7 @@ const int rtc_io_num_map[GPIO_PIN_COUNT] = {
};
//Reg,Mux,Fun,IE,Up,Down,Rtc_number
const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT] = {
const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = {
/*REG MUX select function select Input enable Pullup Pulldown Sleep select Sleep input enable Sleep output enable PAD hold Pad force hold Mask of drive capability Offset gpio number */
{RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD0_HOLD_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_CHANNEL_0_GPIO_NUM}, //0
{RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD1_HOLD_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_CHANNEL_1_GPIO_NUM}, //1

2
components/soc/soc/esp32s2/usb_periph.c
View File

@@ -12,8 +12,8 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/soc_caps.h"
#include "soc/usb_periph.h"
#include "soc/gpio_caps.h"
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},

4
components/soc/soc/esp32s3/gpio_periph.c
View File

@@ -14,7 +14,7 @@
#include "soc/gpio_periph.h"
const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO0_REG,
IO_MUX_GPIO1_REG,
IO_MUX_GPIO2_REG,
@@ -65,7 +65,7 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
0,
};
const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = {
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
0,
0,
0,

16
components/soc/soc/esp32s3/include/soc/adc_caps.h
View File

@@ -19,16 +19,6 @@
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
#define SOC_ADC_MAX_CHANNEL_NUM (10)
#define SOC_ADC1_DATA_INVERT_DEFAULT (0)
#define SOC_ADC2_DATA_INVERT_DEFAULT (0)
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2)
/**
* Check if adc support digital controller (DMA) mode.
* @value
@@ -36,9 +26,3 @@
* - 0 : not support;
*/
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1)

23
components/soc/soc/esp32s3/include/soc/gpio_caps.h
View File

@@ -20,27 +20,18 @@ extern "C" {
// ESP32-S3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define GPIO_PIN_COUNT (48)
#define SOC_GPIO_PIN_COUNT (48)
// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S3
#define GPIO_SUPPORTS_FORCE_HOLD (1)
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
#define GPIO_PRO_CPU_INTR_ENA (BIT(0))
#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(1))
// 0~47 except from 22~25, 47 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47))
// GPIO 46, 47 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47))
#define GPIO_MODE_DEF_DISABLE (0)
#define GPIO_MODE_DEF_INPUT (BIT0)
#define GPIO_MODE_DEF_OUTPUT (BIT1)
#define GPIO_MODE_DEF_OD (BIT2)
#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */
#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_46))) /*!< Check whether it contains input io */
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}

8
components/soc/soc/esp32/include/soc/pcnt_caps.h → components/soc/soc/esp32s3/include/soc/gpio_pins.h
View File

@@ -12,16 +12,16 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32 have 1 PCNT peripheral
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (8)
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#ifdef __cplusplus
}
#endif
#endif

5
components/soc/soc/esp32s3/include/soc/i2c_caps.h
View File

@@ -22,12 +22,11 @@ extern "C" {
#define SOC_I2C_NUM (2)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define I2C_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */
//ESP32-S3 support hardware FSM reset
#define I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
//ESP32-S3 support hardware clear bus
#define I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#ifdef __cplusplus
}

11
components/soc/soc/esp32s3/include/soc/i2s_caps.h
View File

@@ -14,13 +14,10 @@
#pragma once
#define APLL_MIN_FREQ (250000000)
#define APLL_MAX_FREQ (500000000)
#define APLL_I2S_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define I2S_AD_BCK_FACTOR (2)
#define I2S_PDM_BCK_FACTOR (64)
#define I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define I2S_BASE_CLK (2*APB_CLK_FREQ)
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
// ESP32-S3 have 1 I2S
#define SOC_I2S_NUM (1)

4
components/soc/soc/esp32s3/include/soc/rtc_io_caps.h
View File

@@ -14,5 +14,5 @@
#pragma once
#define SOC_RTC_IO_PIN_COUNT 22
#define SOC_PIN_FUNC_RTC_IO 0
#define SOC_RTCIO_PIN_COUNT 22
#define RTCIO_LL_PIN_FUNC 0

12
components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h
View File

@@ -18,20 +18,8 @@ extern "C" {
#endif
// ESP32-S3 have 1 SIGMADELTA peripheral.
#define SIGMADELTA_PORT_0 (0) /*!< SIGMADELTA port 0 */
#define SIGMADELTA_PORT_MAX (1) /*!< SIGMADELTA port max */
#define SOC_SIGMADELTA_NUM (SIGMADELTA_PORT_MAX)
#define SIGMADELTA_CHANNEL_0 (0) /*!< Sigma-delta channel 0 */
#define SIGMADELTA_CHANNEL_1 (1) /*!< Sigma-delta channel 1 */
#define SIGMADELTA_CHANNEL_2 (2) /*!< Sigma-delta channel 2 */
#define SIGMADELTA_CHANNEL_3 (3) /*!< Sigma-delta channel 3 */
#define SIGMADELTA_CHANNEL_4 (4) /*!< Sigma-delta channel 4 */
#define SIGMADELTA_CHANNEL_5 (5) /*!< Sigma-delta channel 5 */
#define SIGMADELTA_CHANNEL_6 (6) /*!< Sigma-delta channel 6 */
#define SIGMADELTA_CHANNEL_7 (7) /*!< Sigma-delta channel 7 */
#define SIGMADELTA_CHANNEL_MAX (8)
#ifdef __cplusplus
}
#endif

67
components/soc/soc/esp32s3/include/soc/soc_caps.h
View File

@@ -1,15 +1,76 @@
// The long term plan is to have a single soc_caps.h for each peripheral.
// The long term plan is to have a single soc_caps.h for all peripherals.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.
// separate these information into periph_caps.h for each peripheral and
// include them here to avoid developing conflicts.
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_TWAI_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_CPU_CORES_NUM 2
#define SOC_CACHE_SUPPORT_WRAP 1
/*-------------------------- ADC CAPS ----------------------------------------*/
#include "adc_caps.h"
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#include "brownout_caps.h"
/*-------------------------- CPU CAPS ----------------------------------------*/
#include "cpu_caps.h"
/*-------------------------- DAC CAPS ----------------------------------------*/
#include "dac_caps.h"
/*-------------------------- GDMA CAPS ---------------------------------------*/
#include "gdma_caps.h"
/*-------------------------- GPIO CAPS ---------------------------------------*/
#include "gpio_caps.h"
/*-------------------------- I2C CAPS ----------------------------------------*/
#include "i2c_caps.h"
/*-------------------------- I2S CAPS ----------------------------------------*/
#include "i2s_caps.h"
/*-------------------------- LEDC CAPS ---------------------------------------*/
#include "ledc_caps.h"
/*-------------------------- MPU CAPS ----------------------------------------*/
#include "mpu_caps.h"
/*-------------------------- PCNT CAPS ---------------------------------------*/
#include "pcnt_caps.h"
/*-------------------------- RMT CAPS ----------------------------------------*/
#include "rmt_caps.h"
/*-------------------------- RTCIO CAPS --------------------------------------*/
#include "rtc_io_caps.h"
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#include "sigmadelta_caps.h"
/*-------------------------- SPI CAPS ----------------------------------------*/
#include "spi_caps.h"
/*-------------------------- SYS TIMER CAPS ----------------------------------*/
#include "systimer_caps.h"
/*-------------------------- TIMER GROUP CAPS --------------------------------*/
#include "timer_group_caps.h"
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#include "touch_sensor_caps.h"
/*-------------------------- TWAI CAPS ---------------------------------------*/
#include "twai_caps.h"
/*-------------------------- UART CAPS ---------------------------------------*/
#include "uart_caps.h"
// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
// Remove them when GDMA driver API is ready
#define SOC_GDMA_M2M_DMA_CHANNEL (0)

19
components/soc/soc/esp32s2/include/soc/brownout_caps.h → components/soc/soc/esp32s3/include/soc/soc_pins.h
View File

@@ -12,14 +12,15 @@
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* Pin definition header file. The long term plan is to have a single soc_pins.h for all
* peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
* peripheral and include them here to avoid developing conflicts in those header files.
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_BROWNOUT_RESET_SUPPORTED 1
#ifdef __cplusplus
}
#endif
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"
#include "soc/sdio_slave_pins.h"
#include "soc/sdmmc_pins.h"

22
components/soc/soc/esp32s3/include/soc/spi_caps.h
View File

@@ -14,30 +14,10 @@
#pragma once
#define SOC_SPI_PERIPH_NUM 4
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_DMA_CHAN_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) 3
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_HD 27
#define SPI_IOMUX_PIN_NUM_CS 29
#define SPI_IOMUX_PIN_NUM_MOSI 32
#define SPI_IOMUX_PIN_NUM_CLK 30
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
//TODO: add the next slot
#define FSPI_FUNC_NUM 4
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
//TODO: add the next slot
//HSPI and VSPI have no iomux pins
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72
//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles

10
components/soc/soc/esp32s3/include/soc/spi_pins.h
View File

@@ -14,22 +14,20 @@
#pragma once
#define SPI_PERIPH_NUM 3
#define SPI_FUNC_NUM 2
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_HD 27
#define SPI_IOMUX_PIN_NUM_CS 29
#define SPI_IOMUX_PIN_NUM_MOSI 32
#define SPI_IOMUX_PIN_NUM_CLK 30
#define SPI_IOMUX_PIN_NUM_MISO 31
#define SPI_IOMUX_PIN_NUM_WP 28
//TODO: add the next slot
#define FSPI_FUNC_NUM 0
#define FSPI_FUNC_NUM 4
#define FSPI_IOMUX_PIN_NUM_HD 9
#define FSPI_IOMUX_PIN_NUM_CS 10
#define FSPI_IOMUX_PIN_NUM_MOSI 11
#define FSPI_IOMUX_PIN_NUM_CLK 12
#define FSPI_IOMUX_PIN_NUM_MISO 13
#define FSPI_IOMUX_PIN_NUM_WP 14
//TODO: add the next slot
//HSPI have no iomux pins

3
components/soc/soc/esp32s3/include/soc/touch_sensor_caps.h
View File

@@ -19,9 +19,8 @@ extern "C" {
#endif
#define SOC_TOUCH_SENSOR_NUM (15)
#define SOC_TOUCH_SENSOR_BIT_MASK_MAX (0x7fff)
#define SOC_TOUCH_PAD_MEASURE_WAIT (0xFF)
#define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF)
#define SOC_TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF)
#define SOC_TOUCH_SHIELD_CHANNEL (14)

4
components/soc/soc/esp32s3/include/soc/twai_caps.h
View File

@@ -18,8 +18,8 @@
extern "C" {
#endif
#define TWAI_BRP_MIN 2
#define TWAI_BRP_MAX 32768
#define SOC_TWAI_BRP_MIN 2
#define SOC_TWAI_BRP_MAX 32768
#ifdef __cplusplus
}

6
components/soc/soc/esp32s3/include/soc/uart_caps.h
View File

@@ -18,13 +18,11 @@
extern "C" {
#endif
#define UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
// ESP32-S3 have 2 UART
#define SOC_UART_NUM (2)
#define SOC_UART_MIN_WAKEUP_THRESH (2)
#define UART_INTR_MASK (0x7ffff) //All interrupt mask
#ifdef __cplusplus
}

4
components/soc/soc/esp32s3/rtc_io_periph.c
View File

@@ -14,7 +14,7 @@
#include "soc/rtc_io_periph.h"
const int rtc_io_num_map[GPIO_PIN_COUNT] = {
const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
RTCIO_GPIO0_CHANNEL, //GPIO0
RTCIO_GPIO1_CHANNEL, //GPIO1
RTCIO_GPIO2_CHANNEL, //GPIO2
@@ -66,7 +66,7 @@ const int rtc_io_num_map[GPIO_PIN_COUNT] = {
};
//Reg,Mux,Fun,IE,Up,Down,Rtc_number
const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT] = {
const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT] = {
/*REG MUX select function select Input enable Pullup Pulldown Sleep select Sleep input enable Sleep output enable PAD hold Pad force hold Mask of drive capability Offset gpio number */
{RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD0_HOLD_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_CHANNEL_0_GPIO_NUM}, //0
{RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD1_HOLD_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_CHANNEL_1_GPIO_NUM}, //1

4
components/soc/soc/include/soc/adc_periph.h
View File

@@ -21,7 +21,7 @@
#include "soc/rtc_io_struct.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/adc_channel.h"
#include "soc/adc_caps.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
@@ -29,7 +29,7 @@ extern "C" {
/**
* Store IO number corresponding to the ADC channel number.
*
*
* @value
* - >=0 : GPIO number index.
* - -1 : Not support.

2
components/soc/soc/include/soc/dac_periph.h
View File

@@ -20,7 +20,7 @@
#include "soc/rtc_io_struct.h"
#include "soc/rtc.h"
#include "soc/dac_channel.h"
#include "soc/dac_caps.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C"

6
components/soc/soc/include/soc/gpio_periph.h
View File

@@ -17,7 +17,7 @@
#include "soc/io_mux_reg.h"
#include "soc/gpio_struct.h"
#include "soc/gpio_reg.h"
#include "soc/gpio_caps.h"
#include "soc/soc_caps.h"
#include "soc/gpio_sig_map.h"
#ifdef __cplusplus
@@ -25,9 +25,9 @@ extern "C"
{
#endif
extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT];
extern const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT];
extern const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT];
extern const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT];
#ifdef __cplusplus
}

2
components/soc/soc/include/soc/i2c_periph.h
View File

@@ -15,7 +15,7 @@
#include "soc/i2c_reg.h"
#include "soc/i2c_struct.h"
#include "soc/i2c_caps.h"
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus

2
components/soc/soc/include/soc/i2s_periph.h
View File

@@ -17,7 +17,7 @@
#include "soc/periph_defs.h"
#include "soc/i2s_struct.h"
#include "soc/i2s_reg.h"
#include "soc/i2s_caps.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {

2
components/soc/soc/include/soc/ledc_periph.h
View File

@@ -13,9 +13,9 @@
// limitations under the License.
#pragma once
#include "soc/soc_caps.h"
#include "soc/ledc_reg.h"
#include "soc/ledc_struct.h"
#include "soc/ledc_caps.h"
#ifdef __cplusplus
extern "C" {

7
components/soc/soc/include/soc/rtc_io_periph.h
View File

@@ -16,14 +16,13 @@
#include "soc/soc.h"
//include soc related (generated) definitions
#include "soc/rtc_io_caps.h"
#include "soc/soc_caps.h"
#include "soc/rtc_io_channel.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_io_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/sens_struct.h"
#include "soc/gpio_caps.h"
#ifdef __cplusplus
extern "C"
@@ -61,7 +60,7 @@ typedef struct {
* This is an internal function of the driver, and is not usually useful
* for external use.
*/
extern const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT];
extern const rtc_io_desc_t rtc_io_desc[SOC_RTCIO_PIN_COUNT];
/**
* @brief Provides a constant table to get rtc io number with gpio number
@@ -69,7 +68,7 @@ extern const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT];
* This is an internal function of the driver, and is not usually useful
* for external use.
*/
extern const int rtc_io_num_map[GPIO_PIN_COUNT];
extern const int rtc_io_num_map[SOC_GPIO_PIN_COUNT];
#ifdef CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC
/**

2
components/soc/soc/include/soc/rtc_periph.h
View File

@@ -15,7 +15,7 @@
#pragma once
#include <stdint.h>
#include "rtc_io_periph.h"
#include "soc/gpio_caps.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C"

2
components/soc/soc/include/soc/sdio_slave_periph.h
View File

@@ -15,7 +15,7 @@
#pragma once
#include <stdint.h>
//include soc related (generated) definitions
#include "soc/sdio_slave_pins.h"
#include "soc/soc_pins.h"
#include "soc/slc_reg.h"
#include "soc/slc_struct.h"
#include "soc/host_reg.h"

2
components/soc/soc/include/soc/sdmmc_periph.h
View File

@@ -15,7 +15,7 @@
#pragma once
#include <stdint.h>
//include soc related (generated) definitions
#include "soc/sdmmc_pins.h"
#include "soc/soc_pins.h"
#include "soc/sdmmc_reg.h"
#include "soc/sdmmc_struct.h"
#include "soc/gpio_sig_map.h"

3
components/soc/soc/include/soc/spi_periph.h
View File

@@ -19,7 +19,8 @@
#include "soc/periph_defs.h"
//include soc related (generated) definitions
#include "soc/spi_caps.h"
#include "soc/soc_caps.h"
#include "soc/soc_pins.h"
#include "soc/spi_reg.h"
#include "soc/spi_struct.h"
#include "soc/gpio_sig_map.h"

2
components/soc/soc/include/soc/touch_sensor_periph.h
View File

@@ -14,8 +14,8 @@
#pragma once
#include "soc/soc_caps.h"
#include "soc/touch_sensor_channel.h"
#include "soc/touch_sensor_caps.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/sens_reg.h"

2
components/soc/soc/include/soc/twai_periph.h
View File

@@ -20,8 +20,8 @@
extern "C" {
#endif
#include "soc/soc_caps.h"
#include "soc/twai_struct.h"
#include "soc/twai_caps.h"
#ifdef __cplusplus
}

2
components/soc/soc/include/soc/uart_periph.h
View File

@@ -13,9 +13,9 @@
#pragma once
#include "soc/soc_caps.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/uart_caps.h"
#include "soc/periph_defs.h"
#include "soc/gpio_sig_map.h"