Merge branch 'feat/psram_bringup_c61' into 'master'

feature(spiram): Bringup spiram for esp32c61, also flash, also .bss .noinit

Closes IDF-9293 and IDF-9294

See merge request espressif/esp-idf!32709

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -107,6 +107,10 @@ config SOC_ECDSA_SUPPORTED
     bool
     default y
 
+config SOC_SPIRAM_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32c61/include/soc/clk_tree_defs.h

@@ -343,6 +343,22 @@ typedef enum {
     LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK,   /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
 } soc_periph_ledc_clk_src_legacy_t;
 
+//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////
+/**
+ * @brief Array initializer for all supported clock sources of MSPI digital controller
+ */
+#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
+/**
+ * @brief MSPI digital controller clock source
+ */
+typedef enum {
+    MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
+    MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
+    MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL,           /*!< Select SPLL as the source clock */
+    MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL,        /*!< Select PLL_F64M as the default clock choice */
+    MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as ROM default clock source */
+} soc_periph_mspi_clk_src_t;
+
 //////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
 typedef enum {
     CLKOUT_SIG_PLL      = 1,    /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */

components/soc/esp32c61/include/soc/io_mux_reg.h

@@ -130,6 +130,7 @@ extern "C" {
 #define SPI_CLK_GPIO_NUM             20
 #define SPI_D_GPIO_NUM               21
 #define SPI_Q_GPIO_NUM               16
+#define SPI_CS1_GPIO_NUM             14
 
 #define USB_INT_PHY0_DM_GPIO_NUM     12
 #define USB_INT_PHY0_DP_GPIO_NUM     13

components/soc/esp32c61/include/soc/soc.h

@@ -192,7 +192,7 @@
 #define SOC_MEM_INTERNAL_LOW1       0x40800000
 #define SOC_MEM_INTERNAL_HIGH1      0x40850000
 
-#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory in the address space
 
 // Region of address space that holds peripherals
 #define SOC_PERIPHERAL_LOW 0x60000000

components/soc/esp32c61/include/soc/soc_caps.h

@@ -68,6 +68,7 @@
 //  \#define SOC_LP_I2C_SUPPORTED            0    //TODO: [ESP32C61] IDF-9330, IDF-9337
 //  \#define SOC_PM_SUPPORTED                1
 #define SOC_ECDSA_SUPPORTED             1
+#define SOC_SPIRAM_SUPPORTED            1
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1