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feat(parlio_tx): support loop transmission

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Chen Jichang
2025-03-18 16:23:34 +08:00
parent 6474fd67ae
commit 65074afc0d
17 changed files with 292 additions and 66 deletions
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2
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -987,7 +987,7 @@ config SOC_PARLIO_TRANS_BIT_ALIGN
bool
default y
config SOC_PARLIO_TX_SIZE_BY_DMA
config SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
bool
default y

2
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -385,7 +385,7 @@
#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define SOC_PARLIO_TX_SIZE_BY_DMA 1 /*!< Transaction length is controlled by DMA instead of indicated by register */
#define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission */
#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1 /*!< Support back up registers before sleep */
#define SOC_PARLIO_SUPPORT_SPI_LCD 1 /*!< Support to drive SPI interfaced LCD */