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refactor(mspi): refactor mspi clock src settings

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This commit is contained in:
Armando
2024-12-03 12:13:00 +08:00
parent 56696866ba
commit 6528ab5971
25 changed files with 196 additions and 161 deletions
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55
components/hal/esp32h2/include/hal/mspi_timing_tuning_ll.h Normal file
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@@ -0,0 +1,55 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
//Timing tuning not applied, and flash has its own clock source. Can change flash clock source
#define MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE 1
/************************** MSPI pll clock configurations **************************/
/*
* @brief Select FLASH clock source
*
* @param mspi_id mspi_id
* @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t`
*/
__attribute__((always_inline))
static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
{
HAL_ASSERT(mspi_id == 0);
switch (clk_src) {
case FLASH_CLK_SRC_XTAL:
PCR.mspi_conf.mspi_clk_sel = 0;
break;
case FLASH_CLK_SRC_RC_FAST:
PCR.mspi_conf.mspi_clk_sel = 1;
break;
case FLASH_CLK_SRC_PLL_F64M:
PCR.mspi_conf.mspi_clk_sel = 2;
break;
case FLASH_CLK_SRC_PLL_F48M:
PCR.mspi_conf.mspi_clk_sel = 3;
break;
default:
HAL_ASSERT(false);
}
}
#ifdef __cplusplus
}
#endif

21
components/hal/esp32h2/include/hal/spimem_flash_ll.h
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@@ -474,27 +474,6 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i
dev->ctrl.val = ctrl.val;
}
__attribute__((always_inline))
static inline void spimem_flash_ll_set_clock_source(soc_periph_mspi_clk_src_t clk_src)
{
switch (clk_src) {
case MSPI_CLK_SRC_XTAL:
PCR.mspi_conf.mspi_clk_sel = 0;
break;
case MSPI_CLK_SRC_RC_FAST:
PCR.mspi_conf.mspi_clk_sel = 1;
break;
case MSPI_CLK_SRC_PLL_F64M:
PCR.mspi_conf.mspi_clk_sel = 2;
break;
case MSPI_CLK_SRC_PLL_F48M:
PCR.mspi_conf.mspi_clk_sel = 3;
break;
default:
HAL_ASSERT(false);
}
}
/**
* Set clock frequency to work at.
*