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refactor(mspi): refactor mspi clock src settings

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This commit is contained in:
Armando
2024-12-03 12:13:00 +08:00
parent 56696866ba
commit 6528ab5971
25 changed files with 196 additions and 161 deletions
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4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -1131,10 +1131,6 @@ config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
config SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2

18
components/soc/esp32c5/include/soc/clk_tree_defs.h
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@@ -488,20 +488,20 @@ typedef enum {
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
} soc_periph_parlio_clk_src_t;
//////////////////////////////////////////////////MSPI///////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////FLASH///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MSPI digital controller
* @brief Array initializer for all supported clock sources of FLASH MSPI controller
*/
#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL}
/**
* @brief MSPI digital controller clock source
* @brief FLASH MSPI controller clock source
*/
typedef enum {
MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */
MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_mspi_clk_src_t;
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
FLASH_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum { // TODO

1
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -461,7 +461,6 @@
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
#define SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
// TODO: [ESP32C5] IDF-8707