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feat(driver_spi): support using SPI_DEVICE_STD_TIMING to adjust master rx in standard timing

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wanckl
2024-12-25 22:10:57 +08:00
parent a83eb05dc0
commit 65a616197f
19 changed files with 281 additions and 14 deletions
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10
components/soc/esp32h2/include/soc/spi_struct.h
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@@ -622,7 +622,15 @@ typedef union {
* In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
*/
uint32_t clkdiv_pre:4;
uint32_t reserved_22:9;
uint32_t reserved_22:8;
/** clk_edge_sel : R/W; bitpos: [30]; default: 0;
* Configures use standard clock sampling edge or delay the sampling edge by half a
* cycle in master transfer.
* 0: clock sampling edge is delayed by half a cycle.
* 1: clock sampling edge is standard.
* Can be configured in CONF state. Only support on chip version >= 1.2
*/
uint32_t clk_edge_sel:1;
/** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
* In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
* clock. Can be configured in CONF state.