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spi: remove HSPI macro on esp32c3 and esp32s3

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This commit is contained in:
Armando
2021-03-05 16:20:33 +08:00
parent 278cfc2047
commit 670b057b04
32 changed files with 185 additions and 190 deletions
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12
components/driver/include/driver/sdspi_host.h
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@@ -28,6 +28,12 @@ extern "C" {
/// Handle representing an SD SPI device
typedef int sdspi_dev_handle_t;
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
#define SDSPI_DEFAULT_HOST HSPI_HOST
#else
#define SDSPI_DEFAULT_HOST SPI2_HOST
#endif
/**
* @brief Default sdmmc_host_t structure initializer for SD over SPI driver
*
@@ -37,7 +43,7 @@ typedef int sdspi_dev_handle_t;
*/
#define SDSPI_HOST_DEFAULT() {\
.flags = SDMMC_HOST_FLAG_SPI | SDMMC_HOST_FLAG_DEINIT_ARG, \
.slot = HSPI_HOST, \
.slot = SDSPI_DEFAULT_HOST, \
.max_freq_khz = SDMMC_FREQ_DEFAULT, \
.io_voltage = 3.3f, \
.init = &sdspi_host_init, \
@@ -71,7 +77,7 @@ typedef struct {
* Macro defining default configuration of SD SPI device.
*/
#define SDSPI_DEVICE_CONFIG_DEFAULT() {\
.host_id = HSPI_HOST, \
.host_id = SDSPI_DEFAULT_HOST, \
.gpio_cs = GPIO_NUM_13, \
.gpio_cd = SDSPI_SLOT_NO_CD, \
.gpio_wp = SDSPI_SLOT_NO_WP, \
@@ -228,7 +234,7 @@ typedef struct {
*
* @note The SDIO over sdspi needs an extra interrupt line. Call ``gpio_install_isr_service()`` before this function.
*
* @param slot SPI controller to use (HSPI_HOST or VSPI_HOST)
* @param slot SPI controller to use (SPI2_HOST or SPI3_HOST)
* @param slot_config pointer to slot configuration structure
* @deprecated Use `sdspi_host_init_device` instead.

2
components/driver/include/driver/spi_common.h
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@@ -119,7 +119,7 @@ typedef struct {
/**
* @brief Initialize a SPI bus
*
* @warning For now, only supports HSPI and VSPI.
* @warning SPI0/1 is not supported
*
* @param host_id SPI peripheral that controls this bus
* @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized

2
components/driver/include/driver/spi_slave.h
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@@ -88,7 +88,7 @@ struct spi_slave_transaction_t {
/**
* @brief Initialize a SPI bus as a slave interface
*
* @warning For now, only supports HSPI and VSPI.
* @warning SPI0/1 is not supported
*
* @param host SPI peripheral to use as a SPI slave interface
* @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized

1
components/driver/spi_slave.c
View File

@@ -119,7 +119,6 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
uint32_t actual_rx_dma_chan = 0;
esp_err_t ret = ESP_OK;
esp_err_t err;
//We only support HSPI/VSPI, period.
SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG);
#ifdef CONFIG_IDF_TARGET_ESP32
SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG );

126
components/driver/test/include/test/test_common_spi.h
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@@ -16,32 +16,29 @@
// All the tests using the header should use this definition as much as possible,
// so that the working host can be changed easily in the future.
#if CONFIG_IDF_TARGET_ESP32
#define TEST_SPI_HOST HSPI_HOST
#define TEST_SLAVE_HOST VSPI_HOST
#define TEST_SPI_HOST SPI2_HOST
#define TEST_SLAVE_HOST SPI3_HOST
#define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD
#define PIN_NUM_MISO SPI2_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK SPI2_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS SPI2_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP SPI2_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD SPI2_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_PIN_NUM_MOSI VSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_PIN_NUM_CLK VSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS
#define SLAVE_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP
#define SLAVE_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD
#define MASTER_IOMUX_PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK SPI2_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS SPI2_IOMUX_PIN_NUM_CS
#define MASTER_IOMUX_PIN_WP SPI2_IOMUX_PIN_NUM_WP
#define MASTER_IOMUX_PIN_HD SPI2_IOMUX_PIN_NUM_HD
#define SLAVE_IOMUX_PIN_MISO VSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_IOMUX_PIN_MOSI VSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_IOMUX_PIN_SCLK VSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_IOMUX_PIN_CS VSPI_IOMUX_PIN_NUM_CS
#define MASTER_IOMUX_PIN_MISO HSPI_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK HSPI_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS HSPI_IOMUX_PIN_NUM_CS
#define SLAVE_IOMUX_PIN_MISO SPI3_IOMUX_PIN_NUM_MISO
#define SLAVE_IOMUX_PIN_MOSI SPI3_IOMUX_PIN_NUM_MOSI
#define SLAVE_IOMUX_PIN_SCLK SPI3_IOMUX_PIN_NUM_CLK
#define SLAVE_IOMUX_PIN_CS SPI3_IOMUX_PIN_NUM_CS
#define SLAVE_IOMUX_PIN_WP SPI3_IOMUX_PIN_NUM_WP
#define SLAVE_IOMUX_PIN_HD SPI3_IOMUX_PIN_NUM_HD
#define UNCONNECTED_PIN 27
#define INPUT_ONLY_PIN 34
@@ -50,34 +47,29 @@
#define WIRE_DELAY 12.5
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define TEST_SPI_HOST SPI2_HOST
#define TEST_SLAVE_HOST SPI3_HOST
#define TEST_SPI_HOST FSPI_HOST
#define TEST_SLAVE_HOST HSPI_HOST
#define PIN_NUM_MISO SPI2_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK SPI2_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS SPI2_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP SPI2_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD SPI2_IOMUX_PIN_NUM_HD
#define PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
#define SLAVE_PIN_NUM_WP -1
#define SLAVE_PIN_NUM_HD -1
#define MASTER_IOMUX_PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK SPI2_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS SPI2_IOMUX_PIN_NUM_CS
#define MASTER_IOMUX_PIN_WP SPI2_IOMUX_PIN_NUM_WP
#define MASTER_IOMUX_PIN_HD SPI2_IOMUX_PIN_NUM_HD
#define SLAVE_IOMUX_PIN_MISO -1
#define SLAVE_IOMUX_PIN_MOSI -1
#define SLAVE_IOMUX_PIN_SCLK -1
#define SLAVE_IOMUX_PIN_CS -1
#define MASTER_IOMUX_PIN_MISO FSPI_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK FSPI_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS FSPI_IOMUX_PIN_NUM_CS
#define SLAVE_IOMUX_PIN_NUM_WP -1
#define SLAVE_IOMUX_PIN_NUM_HD -1
#define UNCONNECTED_PIN 41
#define INPUT_ONLY_PIN 46
@@ -86,40 +78,30 @@
#define WIRE_DELAY 12.5
#elif CONFIG_IDF_TARGET_ESP32C3
#define TEST_SPI_HOST FSPI_HOST
#define TEST_SLAVE_HOST FSPI_HOST
#define PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO -1
#define SLAVE_PIN_NUM_MOSI -1
#define SLAVE_PIN_NUM_CLK -1
#define SLAVE_PIN_NUM_CS -1
#define SLAVE_PIN_NUM_WP -1
#define SLAVE_PIN_NUM_HD -1
//NOTE: On esp32c3, there is only 1 GPSPI controller, so master-slave test on single board should be disabled
#define SLAVE_IOMUX_PIN_MISO FSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_IOMUX_PIN_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_IOMUX_PIN_SCLK FSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_IOMUX_PIN_CS FSPI_IOMUX_PIN_NUM_CS
#define TEST_SPI_HOST SPI2_HOST
#define TEST_SLAVE_HOST SPI2_HOST
#define MASTER_IOMUX_PIN_MISO FSPI_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK FSPI_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS FSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_MISO SPI2_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK SPI2_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS SPI2_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP SPI2_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD SPI2_IOMUX_PIN_NUM_HD
#define SLAVE_IOMUX_PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
#define SLAVE_IOMUX_PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define SLAVE_IOMUX_PIN_SCLK SPI2_IOMUX_PIN_NUM_CLK
#define SLAVE_IOMUX_PIN_CS SPI2_IOMUX_PIN_NUM_CS
#define MASTER_IOMUX_PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
#define MASTER_IOMUX_PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
#define MASTER_IOMUX_PIN_SCLK SPI2_IOMUX_PIN_NUM_CLK
#define MASTER_IOMUX_PIN_CS SPI2_IOMUX_PIN_NUM_CS
#define GPIO_DELAY 0
#define ESP_SPI_SLAVE_TV 0
#define WIRE_DELAY 12.5
#endif
#define GET_DMA_CHAN(HOST) (HOST)

2
components/driver/test/test_sdio.c
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@@ -39,7 +39,7 @@
//TEST_CNT > 512
#define TEST_CNT 10000
#define TEST_SDSPI_HOST HSPI_HOST
#define TEST_SDSPI_HOST SPI2_HOST
#define TEST_SDSPI_DMACHAN 1
#define TEST_RESET_DATA_LEN 10

2
components/driver/test/test_spi_master.c
View File

@@ -474,7 +474,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
}
TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)", "[spi]")
TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)", "[spi]")
{
//spi config
spi_bus_config_t bus_config;

6
components/driver/test/test_spi_slave.c
View File

@@ -224,7 +224,7 @@ static void unaligned_test_slave(void)
unity_wait_for_signal("Master ready");
spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO));
TEST_ESP_OK(spi_slave_initialize(TEST_SPI_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO));
uint8_t *slave_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA);
@@ -248,7 +248,7 @@ static void unaligned_test_slave(void)
};
unity_send_signal("Slave ready");
TEST_ESP_OK(spi_slave_transmit(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY));
TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &slave_t, portMAX_DELAY));
//show result
ESP_LOGI(SLAVE_TAG, "trans_len: %d", slave_t.trans_len);
@@ -265,7 +265,7 @@ static void unaligned_test_slave(void)
free(slave_send_buf);
free(slave_recv_buf);
free(master_send_buf);
TEST_ASSERT(spi_slave_free(TEST_SLAVE_HOST) == ESP_OK);
TEST_ASSERT(spi_slave_free(TEST_SPI_HOST) == ESP_OK);
}
TEST_CASE_MULTIPLE_DEVICES("SPI_Slave_Unaligned_Test", "[spi_ms][test_env=Example_SPI_Multi_device][timeout=120]", unaligned_test_master, unaligned_test_slave);

4
components/driver/test/test_spi_slave_hd.c
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@@ -115,8 +115,8 @@ static void init_slave_hd(int mode, bool append_mode, const spi_slave_hd_callbac
{
spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
bus_cfg.max_transfer_sz = TEST_DMA_MAX_SIZE*30;
bus_cfg.quadwp_io_num = SLAVE_PIN_NUM_WP;
bus_cfg.quadhd_io_num = SLAVE_PIN_NUM_HD;
bus_cfg.quadwp_io_num = -1;
bus_cfg.quadhd_io_num = -1;
#ifdef TEST_SLAVE_GPIO_MATRIX
bus_cfg.flags |= SPICOMMON_BUSFLAG_FORCE_GPIO;
#endif