diff --git a/components/esp_driver_ppa/include/driver/ppa.h b/components/esp_driver_ppa/include/driver/ppa.h index 5f209e85e0..9f019a4557 100644 --- a/components/esp_driver_ppa/include/driver/ppa.h +++ b/components/esp_driver_ppa/include/driver/ppa.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -127,6 +127,7 @@ typedef struct { }; ppa_color_range_t yuv_range; /*!< When the color mode is any YUV color space, this field is to describe its color range */ ppa_color_conv_std_rgb_yuv_t yuv_std; /*!< When the color mode is any YUV color space, this field is to describe its YUV<->RGB conversion standard */ + color_yuv422_pack_order_t yuv422_pack_order; /*!< When the color mode is YUV422, this field is to describe its data pack order */ } ppa_in_pic_blk_config_t; /** @@ -268,7 +269,12 @@ typedef struct { uint32_t fill_block_w; /*!< The width of the block to be filled (unit: pixel) */ uint32_t fill_block_h; /*!< The height of the block to be filled (unit: pixel) */ - color_pixel_argb8888_data_t fill_argb_color; /*!< The color to be filled, in ARGB8888 format */ + union { + color_pixel_argb8888_data_t fill_argb_color; /*!< For any ARGB/RGB format color to be filled, use this field to fill A (if applicable)/R/G/B components */ + color_pixel_gray8_data_t fill_gray8_color; /*!< For GRAY8 format color to be filled */ + color_macroblock_yuv_data_t fill_yuv_color; /*!< For any YUV format color to be filled, use this field to fill Y/U/V components */ + uint32_t fill_color_val; /*!< The color to be filled, in a raw 32-bit value. The interpretation of the value depends on the selected `fill_cm` */ + }; ppa_trans_mode_t mode; /*!< Determines whether to block inside the operation functions, see `ppa_trans_mode_t` */ void *user_data; /*!< User registered data to be passed into `done_cb` callback function */ @@ -287,6 +293,23 @@ typedef struct { */ esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config_t *config); +/** + * @brief Configure the RGB888 to GRAY8 color conversion coefficients for ppa_do_scale_rotate_mirror and ppa_do_fill + * + * The gray value is calculated as: gray = (r_weight * R + g_weight * G + b_weight * B) >> 8 + * Note: (r_weight + g_weight + b_weight) should equal to 256. + * + * @param r_weight Coefficient for R component, range: [0, 255] + * @param g_weight Coefficient for G component, range: [0, 255] + * @param b_weight Coefficient for B component, range: [0, 255] + * @return + * - ESP_OK: Set the RGB888 to GRAY color conversion formula successfully + * - ESP_ERR_NOT_SUPPORTED: Set the RGB888 to GRAY color conversion formula failed because the PPA peripheral does not support this feature + * - ESP_ERR_INVALID_ARG: Set the RGB888 to GRAY color conversion formula failed because of invalid argument + * - ESP_ERR_INVALID_STATE: Set the RGB888 to GRAY color conversion formula failed because the PPA peripheral not initialized + */ +esp_err_t ppa_set_rgb2gray_formula(uint8_t r_weight, uint8_t g_weight, uint8_t b_weight); + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_ppa/src/ppa_blend.c b/components/esp_driver_ppa/src/ppa_blend.c index eec46e560d..7a44dce2df 100644 --- a/components/esp_driver_ppa/src/ppa_blend.c +++ b/components/esp_driver_ppa/src/ppa_blend.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -140,6 +140,13 @@ bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_chann // Configure PPA Blending engine ppa_ll_blend_set_rx_bg_color_mode(platform->hal.dev, blend_trans_desc->in_bg.blend_cm); + if (COLOR_SPACE_TYPE((uint32_t)blend_trans_desc->in_bg.blend_cm) == COLOR_SPACE_YUV) { + ppa_ll_blend_set_rx_bg_yuv_range(platform->hal.dev, blend_trans_desc->in_bg.yuv_range); + ppa_ll_blend_set_rx_bg_yuv2rgb_std(platform->hal.dev, blend_trans_desc->in_bg.yuv_std); + } + if ((uint32_t)blend_trans_desc->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) { + ppa_ll_blend_set_rx_bg_yuv422_pack_order(platform->hal.dev, blend_trans_desc->in_bg.yuv422_pack_order); + } ppa_ll_blend_enable_rx_bg_byte_swap(platform->hal.dev, blend_trans_desc->bg_byte_swap); ppa_ll_blend_enable_rx_bg_rgb_swap(platform->hal.dev, blend_trans_desc->bg_rgb_swap); ppa_ll_blend_configure_rx_bg_alpha(platform->hal.dev, blend_trans_desc->bg_alpha_update_mode, blend_trans_desc->bg_alpha_value); @@ -153,6 +160,10 @@ bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_chann ppa_ll_blend_configure_rx_fg_alpha(platform->hal.dev, blend_trans_desc->fg_alpha_update_mode, blend_trans_desc->fg_alpha_value); ppa_ll_blend_set_tx_color_mode(platform->hal.dev, blend_trans_desc->out.blend_cm); + if (COLOR_SPACE_TYPE((uint32_t)blend_trans_desc->out.blend_cm) == COLOR_SPACE_YUV) { + ppa_ll_blend_set_tx_yuv_range(platform->hal.dev, blend_trans_desc->out.yuv_range); + ppa_ll_blend_set_tx_rgb2yuv_std(platform->hal.dev, blend_trans_desc->out.yuv_std); + } // Color keying color_pixel_rgb888_data_t rgb888_min = {.b = 0x00, .g = 0x00, .r = 0x00}; @@ -182,6 +193,41 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size; ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size"); + ESP_RETURN_ON_FALSE(ppa_ll_blend_is_color_mode_supported(config->in_bg.blend_cm) && ppa_ll_blend_is_color_mode_supported(config->in_fg.blend_cm) && ppa_ll_blend_is_color_mode_supported(config->out.blend_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode"); + // For YUV420 input/output: in desc, ha/hb/va/vb/x/y must be even number + // For YUV422 input/output: in desc, ha/hb/x must be even number + if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV420) { + ESP_RETURN_ON_FALSE(config->in_bg.pic_h % 2 == 0 && config->in_bg.pic_w % 2 == 0 && + config->in_bg.block_h % 2 == 0 && config->in_bg.block_w % 2 == 0 && + config->in_bg.block_offset_x % 2 == 0 && config->in_bg.block_offset_y % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y"); + } else if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->in_bg.pic_w % 2 == 0 && config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); + } + // TODO: Support CLUT to support L4/L8 color mode + // else if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_L4) { + // ESP_RETURN_ON_FALSE(config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, + // ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w and in_bg.block_offset_x must be even"); + // } + if (config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_A4) { // || config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_L4 + ESP_RETURN_ON_FALSE(config->in_fg.block_w % 2 == 0 && config->in_fg.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w and in_fg.block_offset_x must be even"); + } + if (config->out.blend_cm == PPA_BLEND_COLOR_MODE_YUV420) { + ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && + config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); + } else if (config->out.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); + } + ESP_RETURN_ON_FALSE(config->in_bg.block_w <= (config->in_bg.pic_w - config->in_bg.block_offset_x) && + config->in_bg.block_h <= (config->in_bg.pic_h - config->in_bg.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w/h + in_bg.block_offset_x/y does not fit in the in pic"); + ESP_RETURN_ON_FALSE(config->in_fg.block_w <= (config->in_fg.pic_w - config->in_fg.block_offset_x) && + config->in_fg.block_h <= (config->in_fg.pic_h - config->in_fg.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w/h + in_fg.block_offset_x/y does not fit in the in pic"); color_space_pixel_format_t out_pixel_format = { .color_type_id = config->out.blend_cm, }; @@ -190,6 +236,9 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size"); ESP_RETURN_ON_FALSE(config->in_bg.block_w == config->in_fg.block_w && config->in_bg.block_h == config->in_fg.block_h, ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w/h must be equal to in_fg.block_w/h"); + ESP_RETURN_ON_FALSE(config->in_fg.block_w <= (config->out.pic_w - config->out.block_offset_x) && + config->in_fg.block_h <= (config->out.pic_h - config->out.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "block does not fit in the out pic"); if (config->bg_byte_swap) { PPA_CHECK_CM_SUPPORT_BYTE_SWAP("in_bg.blend", (uint32_t)config->in_bg.blend_cm); } @@ -218,15 +267,7 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf ESP_RETURN_ON_FALSE(config->fg_alpha_scale_ratio > 0 && config->fg_alpha_scale_ratio < 1, ESP_ERR_INVALID_ARG, TAG, "invalid fg_alpha_scale_ratio"); new_fg_alpha_value = (uint32_t)(config->fg_alpha_scale_ratio * 256); } - // if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_L4) { - // ESP_RETURN_ON_FALSE(config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0, - // ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w and in_bg.block_offset_x must be even"); - // } - if (config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_A4) { // || config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_L4 - ESP_RETURN_ON_FALSE(config->in_fg.block_w % 2 == 0 && config->in_fg.block_offset_x % 2 == 0, - ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w and in_fg.block_offset_x must be even"); - } - // To reduce complexity, color_mode, alpha_update_mode correctness are checked in their corresponding LL functions + // To reduce complexity, specific color_mode, alpha_update_mode correctness are checked in their corresponding LL functions // Write back and invalidate necessary data (note that the window content is not continuous in the buffer) // Write back in_bg_buffer, in_fg_buffer extended windows (alignment not necessary on C2M direction) diff --git a/components/esp_driver_ppa/src/ppa_core.c b/components/esp_driver_ppa/src/ppa_core.c index 0e40ab195c..4b1ba3c706 100644 --- a/components/esp_driver_ppa/src/ppa_core.c +++ b/components/esp_driver_ppa/src/ppa_core.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -515,3 +515,15 @@ bool ppa_transaction_done_cb(dma2d_channel_handle_t dma2d_chan, dma2d_event_data return need_yield; } + +esp_err_t ppa_set_rgb2gray_formula(uint8_t r_weight, uint8_t g_weight, uint8_t b_weight) +{ + ESP_RETURN_ON_FALSE(ppa_ll_srm_is_color_mode_supported(PPA_SRM_COLOR_MODE_GRAY8) || ppa_ll_blend_is_color_mode_supported(PPA_BLEND_COLOR_MODE_GRAY8), ESP_ERR_NOT_SUPPORTED, TAG, "GRAY color mode not supported"); + ESP_RETURN_ON_FALSE((r_weight + g_weight + b_weight) == 256, ESP_ERR_INVALID_ARG, TAG, "invalid rgb2gray formula"); + ESP_RETURN_ON_FALSE(s_platform.hal.dev, ESP_ERR_INVALID_STATE, TAG, "no PPA client registered yet"); + + _lock_acquire(&s_platform.mutex); + ppa_ll_set_rgb2gray_coeff(s_platform.hal.dev, r_weight, g_weight, b_weight); + _lock_release(&s_platform.mutex); + return ESP_OK; +} diff --git a/components/esp_driver_ppa/src/ppa_fill.c b/components/esp_driver_ppa/src/ppa_fill.c index d8c3aef456..9ec997649b 100644 --- a/components/esp_driver_ppa/src/ppa_fill.c +++ b/components/esp_driver_ppa/src/ppa_fill.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -77,7 +77,7 @@ bool ppa_fill_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channe dma2d_start(dma2d_rx_chan); // Configure PPA Blending engine - ppa_ll_blend_configure_filling_block(platform->hal.dev, &fill_trans_desc->fill_argb_color, fill_trans_desc->fill_block_w, fill_trans_desc->fill_block_h); + ppa_ll_blend_configure_filling_block(platform->hal.dev, fill_trans_desc->out.fill_cm, (void *)&fill_trans_desc->fill_color_val, fill_trans_desc->fill_block_w, fill_trans_desc->fill_block_h); ppa_ll_blend_set_tx_color_mode(platform->hal.dev, fill_trans_desc->out.fill_cm); ppa_ll_blend_start(platform->hal.dev, PPA_LL_BLEND_TRANS_MODE_FILL); @@ -96,13 +96,28 @@ esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size; ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size"); + ESP_RETURN_ON_FALSE(ppa_ll_blend_is_color_mode_supported((ppa_blend_color_mode_t)config->out.fill_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode"); + // For YUV420 output: in desc, ha/hb/va/vb/x/y must be even number + // For YUV422 output: in desc, ha/hb/x must be even number + // if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV420) { + // ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && + // config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, + // ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); + // } else + if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); + } color_space_pixel_format_t out_pixel_format = { .color_type_id = config->out.fill_cm, }; uint32_t out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format); uint32_t out_pic_len = config->out.pic_w * config->out.pic_h * out_pixel_depth / 8; ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size"); - // To reduce complexity, color_mode, fill_block_w/h correctness are checked in their corresponding LL functions + ESP_RETURN_ON_FALSE(config->fill_block_w <= (config->out.pic_w - config->out.block_offset_x) && + config->fill_block_h <= (config->out.pic_h - config->out.block_offset_y), + ESP_ERR_INVALID_ARG, TAG, "block does not fit in the out pic"); + // To reduce complexity, specific color_mode, fill_block_w/h correctness are checked in their corresponding LL functions // Write back and invalidate necessary data (note that the window content is not continuous in the buffer) // Write back and invalidate buffer extended window (alignment not necessary on C2M direction, but alignment strict on M2C direction) diff --git a/components/esp_driver_ppa/src/ppa_priv.h b/components/esp_driver_ppa/src/ppa_priv.h index 6cefafefd2..d335145a45 100644 --- a/components/esp_driver_ppa/src/ppa_priv.h +++ b/components/esp_driver_ppa/src/ppa_priv.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -174,7 +174,12 @@ typedef struct { uint32_t fill_block_w; uint32_t fill_block_h; - color_pixel_argb8888_data_t fill_argb_color; + union { + color_pixel_argb8888_data_t fill_argb_color; + color_pixel_gray8_data_t fill_gray8_color; + color_macroblock_yuv_data_t fill_yuv_color; + uint32_t fill_color_val; + }; ppa_trans_mode_t mode; void *user_data; diff --git a/components/esp_driver_ppa/src/ppa_srm.c b/components/esp_driver_ppa/src/ppa_srm.c index 51849c1c9a..9e48868238 100644 --- a/components/esp_driver_ppa/src/ppa_srm.c +++ b/components/esp_driver_ppa/src/ppa_srm.c @@ -100,13 +100,6 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel dma2d_set_transfer_ability(dma2d_tx_chan, &dma_transfer_ability); dma2d_set_transfer_ability(dma2d_rx_chan, &dma_transfer_ability); - // Configure the block size to be received by the SRM engine, which is passed from the 2D-DMA TX channel (i.e. 2D-DMA dscr-port mode) - dma2d_dscr_port_mode_config_t dma_dscr_port_mode_config = { - .block_h = (srm_trans_desc->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) ? PPA_LL_SRM_YUV420_BLOCK_SIZE : PPA_LL_SRM_DEFAULT_BLOCK_SIZE, - .block_v = (srm_trans_desc->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) ? PPA_LL_SRM_YUV420_BLOCK_SIZE : PPA_LL_SRM_DEFAULT_BLOCK_SIZE, - }; - dma2d_configure_dscr_port_mode(dma2d_tx_chan, &dma_dscr_port_mode_config); - // YUV444 is not supported by PPA module, need to utilize 2D-DMA color space conversion feature to do a conversion ppa_srm_color_mode_t ppa_in_color_mode = srm_trans_desc->in.srm_cm; if (ppa_in_color_mode == PPA_SRM_COLOR_MODE_YUV444) { @@ -129,6 +122,15 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel dma2d_configure_color_space_conversion(dma2d_rx_chan, &dma_rx_csc); } + // Configure the block size to be received by the SRM engine, which is passed from the 2D-DMA TX channel (i.e. 2D-DMA dscr-port mode) + uint32_t block_h = 0, block_v = 0; + ppa_ll_srm_get_dma_dscr_port_mode_block_size(platform->hal.dev, ppa_in_color_mode, ppa_ll_srm_get_mb_size(platform->hal.dev), &block_h, &block_v); + dma2d_dscr_port_mode_config_t dma_dscr_port_mode_config = { + .block_h = block_h, + .block_v = block_v, + }; + dma2d_configure_dscr_port_mode(dma2d_tx_chan, &dma_dscr_port_mode_config); + dma2d_rx_event_callbacks_t dma_event_cbs = { .on_recv_eof = ppa_transaction_done_cb, }; @@ -145,6 +147,9 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel ppa_ll_srm_set_rx_yuv_range(platform->hal.dev, srm_trans_desc->in.yuv_range); ppa_ll_srm_set_rx_yuv2rgb_std(platform->hal.dev, srm_trans_desc->in.yuv_std); } + if ((uint32_t)ppa_in_color_mode == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422)) { + ppa_ll_srm_set_rx_yuv422_pack_order(platform->hal.dev, srm_trans_desc->in.yuv422_pack_order); + } ppa_ll_srm_enable_rx_byte_swap(platform->hal.dev, srm_trans_desc->byte_swap); ppa_ll_srm_enable_rx_rgb_swap(platform->hal.dev, srm_trans_desc->rgb_swap); ppa_ll_srm_configure_rx_alpha(platform->hal.dev, srm_trans_desc->alpha_update_mode, srm_trans_desc->alpha_value); @@ -177,22 +182,25 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size; ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0, ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size"); + ESP_RETURN_ON_FALSE(ppa_ll_srm_is_color_mode_supported(config->in.srm_cm) && ppa_ll_srm_is_color_mode_supported(config->out.srm_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode"); // For YUV420 input/output: in desc, ha/hb/va/vb/x/y must be even number + // For YUV422 input/output: in desc, ha/hb/x must be even number if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { ESP_RETURN_ON_FALSE(config->in.pic_h % 2 == 0 && config->in.pic_w % 2 == 0 && config->in.block_h % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0 && config->in.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y"); + } else if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->in.pic_w % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); } - // TODO: P4 ECO2 support YUV422 - // else if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { - // ESP_RETURN_ON_FALSE(config->in.pic_w % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0, - // ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x"); - // } if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0, ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y"); + } else if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { + ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0, + ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x"); } ESP_RETURN_ON_FALSE(config->in.block_w <= (config->in.pic_w - config->in.block_offset_x) && config->in.block_h <= (config->in.pic_h - config->in.block_offset_y), @@ -232,7 +240,7 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s ESP_RETURN_ON_FALSE(config->alpha_scale_ratio > 0 && config->alpha_scale_ratio < 1, ESP_ERR_INVALID_ARG, TAG, "invalid alpha_scale_ratio"); new_alpha_value = (uint32_t)(config->alpha_scale_ratio * 256); } - // To reduce complexity, rotation_angle, color_mode, alpha_update_mode correctness are checked in their corresponding LL functions + // To reduce complexity, rotation_angle, alpha_update_mode correctness are checked in their corresponding LL functions // Write back and invalidate necessary data (note that the window content is not continuous in the buffer) // Write back in_buffer extended window (alignment not necessary on C2M direction) @@ -270,6 +278,8 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV420) { srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1; srm_trans_desc->scale_y_frag = srm_trans_desc->scale_y_frag & ~1; + } else if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV422) { + srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1; } srm_trans_desc->alpha_value = new_alpha_value; srm_trans_desc->data_burst_length = ppa_client->data_burst_length; diff --git a/components/esp_driver_ppa/test_apps/main/ppa_performance.h b/components/esp_driver_ppa/test_apps/main/ppa_performance.h new file mode 100644 index 0000000000..edab08fc14 --- /dev/null +++ b/components/esp_driver_ppa/test_apps/main/ppa_performance.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "sdkconfig.h" + +/* + * The time spend (T) to complete a PPA transaction is proportional to the amount of pixels (x) need to be processed. + * T = k * x + b + * k = (T - b) / x + */ + +#if CONFIG_IDF_TARGET_ESP32P4 +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (21000 * 1000) // k_min +#define PPA_SRM_TIME_OFFSET (-26000) // b_approx +#else +#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (35000 * 1000) // k_min +#define PPA_SRM_TIME_OFFSET (-37000) // b_approx +#endif + +#define PPA_BLEND_MIN_PERFORMANCE_PX_PER_SEC (31500 * 1000) // k_min +#define PPA_BLEND_TIME_OFFSET (-37150) // b_approx + +#define PPA_FILL_MIN_PERFORMANCE_PX_PER_SEC (150000 * 1000) // k_min +#define PPA_FILL_TIME_OFFSET (-106000) // b_approx +#endif diff --git a/components/esp_driver_ppa/test_apps/main/test_ppa.c b/components/esp_driver_ppa/test_apps/main/test_ppa.c index b1ce989141..5b8dce8b5f 100644 --- a/components/esp_driver_ppa/test_apps/main/test_ppa.c +++ b/components/esp_driver_ppa/test_apps/main/test_ppa.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,7 @@ #include "ccomp_timer.h" #include "hal/color_hal.h" #include "esp_cache.h" +#include "ppa_performance.h" #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) @@ -350,6 +351,39 @@ TEST_CASE("ppa_srm_basic_data_correctness_check", "[PPA]") printf("\n"); TEST_ASSERT_EQUAL_UINT8_ARRAY((void *)out_buf_expected, (void *)out_buf, buf_len); +#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + // Test a rgb2gray color conversion + memset(out_buf, 0, out_buf_size); + esp_cache_msync((void *)out_buf, out_buf_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M); + + const uint8_t r_weight = 100; + const uint8_t g_weight = 56; + const uint8_t b_weight = 100; + TEST_ESP_OK(ppa_set_rgb2gray_formula(r_weight, g_weight, b_weight)); + oper_config.out.srm_cm = PPA_SRM_COLOR_MODE_GRAY8; + oper_config.rotation_angle = PPA_SRM_ROTATION_ANGLE_0; + uint8_t out_buf_expected_gray[16] = {}; + for (int i = 0; i < block_w * block_h; i++) { + const uint16_t pix = in_buf[(i / block_w + in_block_offset_y) * w + (i % block_w + in_block_offset_x)]; + uint8_t _r = ((pix >> 8) & 0xF8); + uint8_t _g = ((pix >> 3) & 0xFC); + uint8_t _b = ((pix << 3) & 0xF8); + out_buf_expected_gray[(i / block_w + out_block_offset_y) * w + (i % block_w + out_block_offset_x)] = (_r * r_weight + _g * g_weight + _b * b_weight) >> 8; + } + + TEST_ESP_OK(ppa_do_scale_rotate_mirror(ppa_client_handle, &oper_config)); + + // Check result + for (int i = 0; i < w * h; i++) { + if (i % 4 == 0) { + printf("\n"); + } + printf("0x%02X ", out_buf[i]); + } + printf("\n"); + TEST_ASSERT_EQUAL_UINT8_ARRAY((void *)out_buf_expected_gray, (void *)out_buf, w * h); +#endif // !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + TEST_ESP_OK(ppa_unregister_client(ppa_client_handle)); free(out_buf); @@ -526,6 +560,20 @@ TEST_CASE("ppa_fill_basic_data_correctness_check", "[PPA]") }; TEST_ASSERT_EACH_EQUAL_UINT16(fill_pixel_expected.val, (void *)((uint32_t)out_buf + w * block_offset_y * out_pixel_depth / 8), block_w * block_h); +#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + // Test a yuv color fill + oper_config.out.fill_cm = PPA_FILL_COLOR_MODE_YUV422; // output YUV422 is with YVYU packed order + const color_macroblock_yuv_data_t fill_yuv_color = {.y = 0xFF, .u = 0x55, .v = 0xAA}; + oper_config.fill_yuv_color = fill_yuv_color; + out_pixel_format.color_type_id = PPA_FILL_COLOR_MODE_YUV422; + out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format); // bits + TEST_ESP_OK(ppa_do_fill(ppa_client_handle, &oper_config)); + + // Check result (2 pixels per macro pixel) + const uint32_t fill_pixel_expected_yuv422 = ((fill_yuv_color.y << 24) | (fill_yuv_color.v << 16) | (fill_yuv_color.y << 8) | (fill_yuv_color.u)); + TEST_ASSERT_EACH_EQUAL_UINT32(fill_pixel_expected_yuv422, (void *)((uint32_t)out_buf + w * block_offset_y * out_pixel_depth / 8), block_w * block_h / 2); +#endif // !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + TEST_ESP_OK(ppa_unregister_client(ppa_client_handle)); free(out_buf); @@ -542,15 +590,6 @@ TEST_CASE("ppa_fill_basic_data_correctness_check", "[PPA]") * k = (T - b) / x */ -#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (21000 * 1000) // k_min -#define PPA_SRM_TIME_OFFSET (-26000) // b_approx - -#define PPA_BLEND_MIN_PERFORMANCE_PX_PER_SEC (31500 * 1000) // k_min -#define PPA_BLEND_TIME_OFFSET (-37150) // b_approx - -#define PPA_FILL_MIN_PERFORMANCE_PX_PER_SEC (150000 * 1000) // k_min -#define PPA_FILL_TIME_OFFSET (-106000) // b_approx - TEST_CASE("ppa_srm_performance", "[PPA]") { // Configurable parameters diff --git a/components/hal/esp32p4/include/hal/ppa_ll.h b/components/hal/esp32p4/include/hal/ppa_ll.h index 017e658daf..76ce8e39c1 100644 --- a/components/hal/esp32p4/include/hal/ppa_ll.h +++ b/components/hal/esp32p4/include/hal/ppa_ll.h @@ -14,6 +14,7 @@ #include "soc/hp_sys_clkrst_struct.h" #include "hal/assert.h" #include "hal/misc.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { @@ -27,9 +28,15 @@ extern "C" { #define PPA_LL_SRM_SCALING_INT_MAX (PPA_SR_SCAL_X_INT_V + 1) #define PPA_LL_SRM_SCALING_FRAG_MAX (PPA_SR_SCAL_X_FRAG_V + 1) -// TODO: On P4 ECO2, SRM block size needs update -#define PPA_LL_SRM_DEFAULT_BLOCK_SIZE 18 // 18 x 18 block size -#define PPA_LL_SRM_YUV420_BLOCK_SIZE 20 // 20 x 20 block size +/** + * @brief Enumeration of PPA SRM macro block size options + */ +typedef enum { + PPA_LL_SRM_MB_SIZE_16_16, /*!< SRM engine processes with a macro block size of 16 x 16 */ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + PPA_LL_SRM_MB_SIZE_32_32, /*!< SRM engine processes with a macro block size of 32 x 32 */ +#endif +} ppa_ll_srm_mb_size_t; /** * @brief Enumeration of PPA blending mode @@ -74,6 +81,29 @@ static inline void ppa_ll_reset_register(void) ppa_ll_reset_register(__VA_ARGS__); \ } while(0) +/** + * @brief Configure the RGB888 to GRAY8 color conversion coefficients for SRM and Blending (excluding Fill) + * + * The gray value is calculated as: gray = (r_coeff * R + g_coeff * G + b_coeff * B) >> 8 + * + * @param dev Peripheral instance address + * @param r_coeff Coefficient for Red channel, range 0-255 + * @param g_coeff Coefficient for Green channel, range 0-255 + * @param b_coeff Coefficient for Blue channel, range 0-255 + */ +static inline void ppa_ll_set_rgb2gray_coeff(ppa_dev_t *dev, uint8_t r_coeff, uint8_t g_coeff, uint8_t b_coeff) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + HAL_ASSERT((r_coeff + g_coeff + b_coeff == 256) && "Sum of RGB to GRAY coefficients must be 256"); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_r, r_coeff); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_g, g_coeff); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_b, b_coeff); +#else + // GRAY8 color mode is not supported by PPA hardware before P4 ECO5 + abort(); +#endif +} + ///////////////////////// Scaling, Rotating, Mirroring (SRM) ////////////////////////////// /** * @brief Reset PPA scaling-rotating-mirroring engine @@ -175,6 +205,30 @@ static inline void ppa_ll_srm_start(ppa_dev_t *dev) dev->sr_scal_rotate.scal_rotate_start = 1; } +/** + * @brief Check if the given color mode is supported by PPA SRM engine + * + * @param color_mode One of the values in ppa_srm_color_mode_t + * @return true if supported; false if not supported + */ +static inline bool ppa_ll_srm_is_color_mode_supported(ppa_srm_color_mode_t color_mode) +{ + switch (color_mode) { + case PPA_SRM_COLOR_MODE_ARGB8888: + case PPA_SRM_COLOR_MODE_RGB888: + case PPA_SRM_COLOR_MODE_RGB565: + case PPA_SRM_COLOR_MODE_YUV420: + case PPA_SRM_COLOR_MODE_YUV444: // YUV444 not supported by PPA hardware, but can be converted by 2D-DMA before/after PPA +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_SRM_COLOR_MODE_YUV422: + case PPA_SRM_COLOR_MODE_GRAY8: +#endif + return true; + default: + return false; + } +} + /** * @brief Set the source image color mode for PPA Scaling-Rotating-Mirroring engine RX * @@ -197,6 +251,14 @@ static inline void ppa_ll_srm_set_rx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo case PPA_SRM_COLOR_MODE_YUV420: val = 8; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_SRM_COLOR_MODE_YUV422: + val = 9; + break; + case PPA_SRM_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported SRM rx color mode abort(); @@ -226,6 +288,14 @@ static inline void ppa_ll_srm_set_tx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo case PPA_SRM_COLOR_MODE_YUV420: val = 8; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_SRM_COLOR_MODE_YUV422: + val = 9; + break; + case PPA_SRM_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported SRM tx color mode abort(); @@ -317,6 +387,38 @@ static inline void ppa_ll_srm_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t } } +/** + * @brief Set PPA SRM input side YUV422 data format packing order + * + * @param dev Peripheral instance address + * @param pack_order One of the pack order options in color_yuv422_pack_order_t + */ +static inline void ppa_ll_srm_set_rx_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (pack_order) { + case COLOR_YUV422_PACK_ORDER_YVYU: + dev->sr_color_mode.yuv422_rx_byte_order = 0; + break; + case COLOR_YUV422_PACK_ORDER_YUYV: + dev->sr_color_mode.yuv422_rx_byte_order = 1; + break; + case COLOR_YUV422_PACK_ORDER_VYUY: + dev->sr_color_mode.yuv422_rx_byte_order = 2; + break; + case COLOR_YUV422_PACK_ORDER_UYVY: + dev->sr_color_mode.yuv422_rx_byte_order = 3; + break; + default: + // Unsupported YUV422 pack order + abort(); + } +#else + // YUV422 not supported by PPA SRM hardware before P4 ECO5 + abort(); +#endif +} + /** * @brief Enable PPA SRM input data swap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR) * @@ -377,6 +479,112 @@ static inline void ppa_ll_srm_configure_rx_alpha(ppa_dev_t *dev, ppa_alpha_updat } } +/** + * @brief Get the current configured PPA SRM macro block size + * + * @param dev Peripheral instance address + * @return The current configured macro block size, one of the values in ppa_ll_srm_mb_size_t + */ +static inline ppa_ll_srm_mb_size_t ppa_ll_srm_get_mb_size(ppa_dev_t *dev) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + return (dev->sr_byte_order.sr_bk_size_sel == 0) ? PPA_LL_SRM_MB_SIZE_32_32 : PPA_LL_SRM_MB_SIZE_16_16; +#else + return PPA_LL_SRM_MB_SIZE_16_16; +#endif +} + +/** + * @brief Set PPA SRM macro block size + * + * @param dev Peripheral instance address + * @param mb_size Macro block size to be set, one of the values in ppa_ll_srm_mb_size_t + */ +static inline void ppa_ll_srm_set_mb_size(ppa_dev_t *dev, ppa_ll_srm_mb_size_t mb_size) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (mb_size) { + case PPA_LL_SRM_MB_SIZE_16_16: + dev->sr_byte_order.sr_bk_size_sel = 1; + break; + case PPA_LL_SRM_MB_SIZE_32_32: + dev->sr_byte_order.sr_bk_size_sel = 0; + break; + default: + // Unsupported SRM macro block size + abort(); + } +#else + HAL_ASSERT(mb_size == PPA_LL_SRM_MB_SIZE_16_16); +#endif +} + +/** + * @brief Retrieve the 2D-DMA descriptor port mode block size (in pixel) according to the PPA SRM input color mode and configured macro block size + * + * @param dev Peripheral instance address + * @param in_color_mode Input color mode, one of the values in ppa_srm_color_mode_t + * @param mb_size SRM macro block size, one of the values in ppa_ll_srm_mb_size_t + * @param[out] block_h Returned block horizontal width + * @param[out] block_v Returned block wvertical height + */ +static inline void ppa_ll_srm_get_dma_dscr_port_mode_block_size(ppa_dev_t *dev, ppa_srm_color_mode_t in_color_mode, ppa_ll_srm_mb_size_t mb_size, uint32_t *block_h, uint32_t *block_v) +{ + if (mb_size == PPA_LL_SRM_MB_SIZE_16_16) { + switch (in_color_mode) { + case PPA_SRM_COLOR_MODE_ARGB8888: + case PPA_SRM_COLOR_MODE_RGB888: + case PPA_SRM_COLOR_MODE_RGB565: + case PPA_SRM_COLOR_MODE_GRAY8: + *block_h = 18; + *block_v = 18; + break; + case PPA_SRM_COLOR_MODE_YUV420: + *block_h = 20; + *block_v = 18; + break; + case PPA_SRM_COLOR_MODE_YUV422: + *block_h = 20; + *block_v = 20; + break; + default: + // Unsupported SRM input color mode + *block_h = 0; + *block_v = 0; + } + } +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + else if (mb_size == PPA_LL_SRM_MB_SIZE_32_32) { + switch (in_color_mode) { + case PPA_SRM_COLOR_MODE_ARGB8888: + case PPA_SRM_COLOR_MODE_RGB888: + case PPA_SRM_COLOR_MODE_RGB565: + case PPA_SRM_COLOR_MODE_GRAY8: + *block_h = 34; + *block_v = 34; + break; + case PPA_SRM_COLOR_MODE_YUV420: + *block_h = 36; + *block_v = 34; + break; + case PPA_SRM_COLOR_MODE_YUV422: + *block_h = 36; + *block_v = 36; + break; + default: + // Unsupported SRM input color mode + *block_h = 0; + *block_v = 0; + } + } +#endif + else { + // Unsupported SRM macro block size + *block_h = 0; + *block_v = 0; + } +} + //////////////////////////////////// Blending //////////////////////////////////////// /* * Alpha Blending Calculation: @@ -426,6 +634,33 @@ static inline void ppa_ll_blend_start(ppa_dev_t *dev, ppa_ll_blend_trans_mode_t dev->blend_trans_mode.blend_trans_mode_update = 1; } +/** + * @brief Check if the given color mode is supported by PPA blending engine + * + * @param color_mode One of the values in ppa_blend_color_mode_t + * @return true if supported (by any of rx_bg, rx_fg, tx); false if not supported + */ +static inline bool ppa_ll_blend_is_color_mode_supported(ppa_blend_color_mode_t color_mode) +{ + switch (color_mode) { + case PPA_BLEND_COLOR_MODE_ARGB8888: + case PPA_BLEND_COLOR_MODE_RGB888: + case PPA_BLEND_COLOR_MODE_RGB565: + case PPA_BLEND_COLOR_MODE_A8: + case PPA_BLEND_COLOR_MODE_A4: + // case PPA_BLEND_COLOR_MODE_L8: + // case PPA_BLEND_COLOR_MODE_L4: +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_BLEND_COLOR_MODE_YUV420: + case PPA_BLEND_COLOR_MODE_YUV422: + case PPA_BLEND_COLOR_MODE_GRAY8: +#endif + return true; + default: + return false; + } +} + /** * @brief Set the source image color mode for background for PPA blending engine RX * @@ -451,6 +686,17 @@ static inline void ppa_ll_blend_set_rx_bg_color_mode(ppa_dev_t *dev, ppa_blend_c // case PPA_BLEND_COLOR_MODE_L4: // val = 5; // break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_BLEND_COLOR_MODE_YUV420: + val = 8; + break; + case PPA_BLEND_COLOR_MODE_YUV422: + val = 9; + break; + case PPA_BLEND_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported blending rx background color mode abort(); @@ -515,6 +761,17 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo case PPA_BLEND_COLOR_MODE_RGB565: val = 2; break; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + case PPA_BLEND_COLOR_MODE_YUV420: + val = 8; + break; + case PPA_BLEND_COLOR_MODE_YUV422: + val = 9; + break; + case PPA_BLEND_COLOR_MODE_GRAY8: + val = 12; + break; +#endif default: // Unsupported blending tx color mode abort(); @@ -522,6 +779,142 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo dev->blend_color_mode.blend_tx_cm = val; } +/** + * @brief Set YUV to RGB protocol when PPA blending source image background pixel color space is YUV + * + * @param dev Peripheral instance address + * @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv2rgb_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (std) { + case PPA_COLOR_CONV_STD_RGB_YUV_BT601: + dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 0; + break; + case PPA_COLOR_CONV_STD_RGB_YUV_BT709: + dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 1; + break; + default: + // Unsupported RGB-YUV conversion standard + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set RGB to YUV protocol when PPA blending destination image pixel color space is YUV + * + * @param dev Peripheral instance address + * @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t + */ +static inline void ppa_ll_blend_set_tx_rgb2yuv_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (std) { + case PPA_COLOR_CONV_STD_RGB_YUV_BT601: + dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 0; + break; + case PPA_COLOR_CONV_STD_RGB_YUV_BT709: + dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 1; + break; + default: + // Unsupported RGB-YUV conversion standard + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set PPA blending source image background YUV input range + * + * @param dev Peripheral instance address + * @param range One of color range options in ppa_color_range_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv_range(ppa_dev_t *dev, ppa_color_range_t range) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (range) { + case PPA_COLOR_RANGE_LIMIT: + dev->blend_color_mode.blend0_rx_yuv_range = 0; + break; + case PPA_COLOR_RANGE_FULL: + dev->blend_color_mode.blend0_rx_yuv_range = 1; + break; + default: + // Unsupported color range + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set PPA blending destination image YUV output range + * + * @param dev Peripheral instance address + * @param range One of color range options in ppa_color_range_t + */ +static inline void ppa_ll_blend_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t range) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (range) { + case PPA_COLOR_RANGE_LIMIT: + dev->blend_color_mode.blend_tx_yuv_range = 0; + break; + case PPA_COLOR_RANGE_FULL: + dev->blend_color_mode.blend_tx_yuv_range = 1; + break; + default: + // Unsupported color range + abort(); + } +#else + // YUV not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + +/** + * @brief Set PPA blending source image background YUV422 data format packing order + * + * @param dev Peripheral instance address + * @param pack_order One of the pack order options in color_yuv422_pack_order_t + */ +static inline void ppa_ll_blend_set_rx_bg_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + switch (pack_order) { + case COLOR_YUV422_PACK_ORDER_YVYU: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 0; + break; + case COLOR_YUV422_PACK_ORDER_YUYV: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 1; + break; + case COLOR_YUV422_PACK_ORDER_VYUY: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 2; + break; + case COLOR_YUV422_PACK_ORDER_UYVY: + dev->blend_color_mode.blend0_rx_yuv422_byte_order = 3; + break; + default: + // Unsupported YUV422 pack order + abort(); + } +#else + // YUV422 not supported by PPA blending hardware before P4 ECO5 + abort(); +#endif +} + /** * @brief Enable PPA blending input background data wrap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR) * @@ -645,15 +1038,44 @@ static inline void ppa_ll_blend_configure_rx_fg_alpha(ppa_dev_t *dev, ppa_alpha_ /** * @brief Configure PPA blending pixel filling image block * + * The color to be filled is directly relying on the blend_tx_fix_pixel register field value. + * For fill operation, the data does not go through any color space conversion in the blending engine. + * * @param dev Peripheral instance address - * @param data The fix data to be filled to the image block pixels in ARGB8888 format + * @param color_mode One of the values in ppa_fill_color_mode_t + * @param data The point of the fix data to be filled to the image block pixels * @param hb The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel. * @param vb The vertical height of image block that would be filled in fix pixel filling mode. The unit is pixel. */ -static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, color_pixel_argb8888_data_t *data, uint32_t hb, uint32_t vb) +static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, ppa_fill_color_mode_t color_mode, void *data, uint32_t hb, uint32_t vb) { HAL_ASSERT(hb <= PPA_BLEND_HB_V && vb <= PPA_BLEND_VB_V); - dev->blend_fix_pixel.blend_tx_fix_pixel = data->val; + uint32_t fill_color_data = 0; + switch (color_mode) { + case PPA_FILL_COLOR_MODE_ARGB8888: + case PPA_FILL_COLOR_MODE_RGB888: + case PPA_FILL_COLOR_MODE_RGB565: + case PPA_FILL_COLOR_MODE_GRAY8: + fill_color_data = *(uint32_t *)data; + break; + case PPA_FILL_COLOR_MODE_YUV422: { + color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data; + fill_color_data = ((yuv_data->y) << 24) | ((yuv_data->v) << 16) | ((yuv_data->y) << 8) | (yuv_data->u); + break; + } + // case PPA_FILL_COLOR_MODE_YUV420: { + // color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data; + // if (yuv_data->u != yuv_data->v) { + // abort(); + // } + // fill_color_data = ((yuv_data->y) << 16) | ((yuv_data->y) << 8) | (yuv_data->v); + // break; + // } + default: + // Unsupported filling color mode + abort(); + } + dev->blend_fix_pixel.blend_tx_fix_pixel = fill_color_data; dev->blend_tx_size.blend_hb = hb; dev->blend_tx_size.blend_vb = vb; } diff --git a/components/hal/include/hal/color_types.h b/components/hal/include/hal/color_types.h index 93c69b323d..b222db3abf 100644 --- a/components/hal/include/hal/color_types.h +++ b/components/hal/include/hal/color_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -179,10 +179,13 @@ typedef union { /** * @brief Data structure for RGB888 pixel unit */ -typedef struct { - uint8_t b; /*!< B component [0, 255] */ - uint8_t g; /*!< G component [0, 255] */ - uint8_t r; /*!< R component [0, 255] */ +typedef union { + struct { + uint8_t b; /*!< B component [0, 255] */ + uint8_t g; /*!< G component [0, 255] */ + uint8_t r; /*!< R component [0, 255] */ + }; + uint32_t val; /*!< 32-bit RGB888 value */ } color_pixel_rgb888_data_t; /** @@ -197,6 +200,29 @@ typedef union { uint16_t val; /*!< 16-bit RGB565 value */ } color_pixel_rgb565_data_t; +/** + * @brief Data structure for GRAY8 pixel unit + */ +typedef union { + struct { + uint8_t gray; /*!< Gray component [0, 255] */ + }; + uint8_t val; /*!< 8-bit GRAY8 value */ +} color_pixel_gray8_data_t; + +/** + * @brief Data structure for YUV macroblock unit + * + * For YUV420, a macroblock is 2x2 pixels + * For YUV422, a macroblock is 2x1 pixels + * For YUV444, a macro block is a 1x1 pixel + */ +typedef struct { + uint8_t y; /*!< Y component [0, 255] */ + uint8_t u; /*!< U component [0, 255] */ + uint8_t v; /*!< V component [0, 255] */ +} color_macroblock_yuv_data_t; + /*--------------------------------------------------------------- Color Components ---------------------------------------------------------------*/ diff --git a/components/hal/include/hal/dma2d_types.h b/components/hal/include/hal/dma2d_types.h index 82b2e64107..3e9142f2e2 100644 --- a/components/hal/include/hal/dma2d_types.h +++ b/components/hal/include/hal/dma2d_types.h @@ -236,23 +236,23 @@ typedef enum { typedef enum { DMA2D_CSC_RX_NONE, /*!< 2D-DMA RX perform no CSC */ DMA2D_CSC_RX_SCRAMBLE, /*!< 2D-DMA RX perform only data scramble */ - DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422 to YUV444-MIPI conversion */ - DMA2D_CSC_RX_YUV422_TO_YUV420, /*!< 2D-DMA RX perform YUV422 to YUV420-MIPI conversion */ - DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420 to YUV444-MIPI conversion */ - DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB888_601, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV444_TO_YUV422, /*!< 2D-DMA RX perform YUV444 to YUV422-MIPI conversion */ - DMA2D_CSC_RX_YUV444_TO_YUV420, /*!< 2D-DMA RX perform YUV444 to YUV420-MIPI conversion */ - DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT601 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT709 standard) */ - DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422-JPEG to YUV444 conversion */ + DMA2D_CSC_RX_YUV422_TO_YUV420, /*!< 2D-DMA RX perform YUV422-JPEG to YUV420 conversion */ + DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420-JPEG to YUV444 conversion */ + DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB888_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV444_TO_YUV422, /*!< 2D-DMA RX perform YUV444-JPEG to YUV422-MIPI conversion */ + DMA2D_CSC_RX_YUV444_TO_YUV420, /*!< 2D-DMA RX perform YUV444-JPEG to YUV420 conversion */ + DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT601 standard) */ + DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT709 standard) */ + DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT709 standard) */ DMA2D_CSC_RX_INVALID, /*!< Invalid 2D-DMA RX color space conversion */ } dma2d_csc_rx_option_t; diff --git a/components/hal/include/hal/ppa_types.h b/components/hal/include/hal/ppa_types.h index 67741433c5..dd967e4218 100644 --- a/components/hal/include/hal/ppa_types.h +++ b/components/hal/include/hal/ppa_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -44,8 +44,8 @@ typedef enum { // YUV444 not supported by PPA hardware, but we can use 2D-DMA to do conversion before sending into and after coming out from the PPA module // If in_pic is YUV444, then TX DMA channel could do DMA2D_CSC_TX_YUV444_TO_RGB888_601/709, so PPA in_color_mode is RGB888 // If out_pic is YUV444, then RX DMA channel could do DMA2D_CSC_RX_YUV420_TO_YUV444, so PPA out_color_mode is YUV420 - // TODO: P4 ECO2 supports YUV422 - // PPA_SRM_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA SRM color mode: YUV422 (input only, limited range only) */ + PPA_SRM_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA SRM color mode: YUV422 (input data pack order all supported, but output data format is fixed to YVYU) */ + PPA_SRM_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA SRM color mode: GRAY8 */ } ppa_srm_color_mode_t; /** @@ -57,9 +57,12 @@ typedef enum { PPA_BLEND_COLOR_MODE_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< PPA blend color mode: RGB565 */ PPA_BLEND_COLOR_MODE_A8 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A8), /*!< PPA blend color mode: A8, only available on blend foreground input */ PPA_BLEND_COLOR_MODE_A4 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A4), /*!< PPA blend color mode: A4, only available on blend foreground input */ + PPA_BLEND_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA blend color mode: YUV420, only available on blend background input or on output */ + PPA_BLEND_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA blend color mode: YUV422, only available on blend background input (all pack order supported) or on output (fixed to YVYU) */ + PPA_BLEND_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA blend color mode: GRAY8, only available on blend background input or on output */ // TODO: Support CLUT to support L4/L8 color mode - // PPA_BLEND_COLOR_MODE_L8 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L8), /*!< PPA blend color mode: L8, only available on blend inputs */ - // PPA_BLEND_COLOR_MODE_L4 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L4), /*!< PPA blend color mode: L4, only available on blend inputs */ + // PPA_BLEND_COLOR_MODE_L8 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L8), /*!< PPA blend color mode: L8, only available on blend input */ + // PPA_BLEND_COLOR_MODE_L4 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L4), /*!< PPA blend color mode: L4, only available on blend input */ } ppa_blend_color_mode_t; /** @@ -69,6 +72,9 @@ typedef enum { PPA_FILL_COLOR_MODE_ARGB8888 = COLOR_TYPE_ID(COLOR_SPACE_ARGB, COLOR_PIXEL_ARGB8888), /*!< PPA fill color mode: ARGB8888 */ PPA_FILL_COLOR_MODE_RGB888 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB888), /*!< PPA fill color mode: RGB888 */ PPA_FILL_COLOR_MODE_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< PPA fill color mode: RGB565 */ + // PPA_FILL_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA fill color mode: YUV420 */ // Non-typical YUV420, U and V components have to be the same value + PPA_FILL_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA fill color mode: YUV422 (w/ YVYU pack order) */ + PPA_FILL_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA fill color mode: GRAY8 */ } ppa_fill_color_mode_t; /** diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h deleted file mode 100644 index 4d0f664733..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h +++ /dev/null @@ -1,1025 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Configuration Registers */ -/** Type of blend0_clut_data register - * CLUT sram data read/write register in background plane of blender - */ -typedef union { - struct { - /** rdwr_word_blend0_clut : R/W; bitpos: [31:0]; default: 0; - * Write and read data to/from CLUT RAM in background plane of blender engine through - * this field in fifo mode. - */ - uint32_t rdwr_word_blend0_clut:32; - }; - uint32_t val; -} ppa_blend0_clut_data_reg_t; - -/** Type of blend1_clut_data register - * CLUT sram data read/write register in foreground plane of blender - */ -typedef union { - struct { - /** rdwr_word_blend1_clut : R/W; bitpos: [31:0]; default: 0; - * Write and read data to/from CLUT RAM in foreground plane of blender engine through - * this field in fifo mode. - */ - uint32_t rdwr_word_blend1_clut:32; - }; - uint32_t val; -} ppa_blend1_clut_data_reg_t; - -/** Type of clut_conf register - * CLUT configure register - */ -typedef union { - struct { - /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; - * 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register - * PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: - * memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr - * should be 01 to access sr clut and should be 10 to access blend0 clut and should be - * 11 to access blend 1 clut in memory mode. - */ - uint32_t apb_fifo_mask:1; - /** blend0_clut_mem_rst : R/W; bitpos: [1]; default: 0; - * Write 1 then write 0 to this bit to reset BLEND0 CLUT. - */ - uint32_t blend0_clut_mem_rst:1; - /** blend1_clut_mem_rst : R/W; bitpos: [2]; default: 0; - * Write 1 then write 0 to this bit to reset BLEND1 CLUT. - */ - uint32_t blend1_clut_mem_rst:1; - /** blend0_clut_mem_rdaddr_rst : R/W; bitpos: [3]; default: 0; - * Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. - */ - uint32_t blend0_clut_mem_rdaddr_rst:1; - /** blend1_clut_mem_rdaddr_rst : R/W; bitpos: [4]; default: 0; - * Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. - */ - uint32_t blend1_clut_mem_rdaddr_rst:1; - /** blend0_clut_mem_force_pd : R/W; bitpos: [5]; default: 0; - * 1: force power down BLEND CLUT memory. - */ - uint32_t blend0_clut_mem_force_pd:1; - /** blend0_clut_mem_force_pu : R/W; bitpos: [6]; default: 0; - * 1: force power up BLEND CLUT memory. - */ - uint32_t blend0_clut_mem_force_pu:1; - /** blend0_clut_mem_clk_ena : R/W; bitpos: [7]; default: 0; - * 1: Force clock on for BLEND CLUT memory. - */ - uint32_t blend0_clut_mem_clk_ena:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} ppa_clut_conf_reg_t; - -/** Type of sr_color_mode register - * Scaling and rotating engine color mode register - */ -typedef union { - struct { - /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0; - * The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: - * RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. - */ - uint32_t sr_rx_cm:4; - /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0; - * The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. - * 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. - */ - uint32_t sr_tx_cm:4; - /** yuv_rx_range : R/W; bitpos: [8]; default: 0; - * YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range - */ - uint32_t yuv_rx_range:1; - /** yuv_tx_range : R/W; bitpos: [9]; default: 0; - * YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range - */ - uint32_t yuv_tx_range:1; - /** yuv2rgb_protocal : R/W; bitpos: [10]; default: 0; - * YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 - */ - uint32_t yuv2rgb_protocal:1; - /** rgb2yuv_protocal : R/W; bitpos: [11]; default: 0; - * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 - */ - uint32_t rgb2yuv_protocal:1; - /** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY - */ - uint32_t yuv422_rx_byte_order:2; - uint32_t reserved_14:18; - }; - uint32_t val; -} ppa_sr_color_mode_reg_t; - -/** Type of blend_color_mode register - * blending engine color mode register - */ -typedef union { - struct { - /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0; - * The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY - */ - uint32_t blend0_rx_cm:4; - /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0; - * The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. - */ - uint32_t blend1_rx_cm:4; - /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0; - * The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY - */ - uint32_t blend_tx_cm:4; - /** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0; - * YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range - */ - uint32_t blend0_rx_yuv_range:1; - /** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0; - * YUV output range when blend tx cm is yuv. 0: limit range. 1: full range - */ - uint32_t blend_tx_yuv_range:1; - /** blend0_rx_yuv2rgb_protocal : R/W; bitpos: [14]; default: 0; - * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 - */ - uint32_t blend0_rx_yuv2rgb_protocal:1; - /** blend_tx_rgb2yuv_protocal : R/W; bitpos: [15]; default: 0; - * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 - */ - uint32_t blend_tx_rgb2yuv_protocal:1; - /** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0; - * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY - */ - uint32_t blend0_rx_yuv422_byte_order:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} ppa_blend_color_mode_reg_t; - -/** Type of sr_byte_order register - * Scaling and rotating engine byte order register - */ -typedef union { - struct { - /** sr_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 - * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - */ - uint32_t sr_rx_byte_swap_en:1; - /** sr_rx_rgb_swap_en : R/W; bitpos: [1]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb - * would be swap to bgr. - */ - uint32_t sr_rx_rgb_swap_en:1; - /** sr_macro_bk_ro_bypass : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to bypass the macro block order function. This function is used - * to improve efficient accessing external memory. - */ - uint32_t sr_macro_bk_ro_bypass:1; - /** sr_bk_size_sel : R/W; bitpos: [3]; default: 0; - * sel srm pix_blk size, 0:32x32, 1:16x16 - */ - uint32_t sr_bk_size_sel:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_sr_byte_order_reg_t; - -/** Type of blend_byte_order register - * Blending engine byte order register - */ -typedef union { - struct { - /** blend0_rx_byte_swap_en : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 - * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - */ - uint32_t blend0_rx_byte_swap_en:1; - /** blend1_rx_byte_swap_en : R/W; bitpos: [1]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 - * and Byte1 would be swapped while byte 2 and byte 3 would be swappped. - */ - uint32_t blend1_rx_byte_swap_en:1; - /** blend0_rx_rgb_swap_en : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb - * would be swap to bgr. - */ - uint32_t blend0_rx_rgb_swap_en:1; - /** blend1_rx_rgb_swap_en : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb - * would be swap to bgr. - */ - uint32_t blend1_rx_rgb_swap_en:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_blend_byte_order_reg_t; - -/** Type of blend_trans_mode register - * Blending engine mode configure register - */ -typedef union { - struct { - /** blend_en : R/W; bitpos: [0]; default: 0; - * Set this bit to enable alpha blending. - */ - uint32_t blend_en:1; - /** blend_bypass : R/W; bitpos: [1]; default: 0; - * Set this bit to bypass blender. Then background date would be output. - */ - uint32_t blend_bypass:1; - /** blend_fix_pixel_fill_en : R/W; bitpos: [2]; default: 0; - * This bit is used to enable fix pixel filling. When this mode is enable only Tx - * channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. - */ - uint32_t blend_fix_pixel_fill_en:1; - /** blend_trans_mode_update : WT; bitpos: [3]; default: 0; - * Set this bit to update the transfer mode. Only the bit is set the transfer mode is - * valid. - */ - uint32_t blend_trans_mode_update:1; - /** blend_rst : R/W; bitpos: [4]; default: 0; - * write 1 then write 0 to reset blending engine. - */ - uint32_t blend_rst:1; - /** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0; - * unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and - * ls_enc - */ - uint32_t blend_tx_inf_sel:2; - uint32_t reserved_7:25; - }; - uint32_t val; -} ppa_blend_trans_mode_reg_t; - -/** Type of sr_fix_alpha register - * Scaling and rotating engine alpha override register - */ -typedef union { - struct { - /** sr_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; - * The value would replace the alpha value in received pixel for Scaling and Rotating - * engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. - */ - uint32_t sr_rx_fix_alpha:8; - /** sr_rx_alpha_mod : R/W; bitpos: [9:8]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. - */ - uint32_t sr_rx_alpha_mod:2; - /** sr_rx_alpha_inv : R/W; bitpos: [10]; default: 0; - * Set this bit to invert the original alpha value. When RX color mode is - * RGB565/RGB88. The original alpha value is 255. - */ - uint32_t sr_rx_alpha_inv:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} ppa_sr_fix_alpha_reg_t; - -/** Type of blend_tx_size register - * Fix pixel filling mode image size register - */ -typedef union { - struct { - /** blend_hb : R/W; bitpos: [13:0]; default: 0; - * The horizontal width of image block that would be filled in fix pixel filling mode - * or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420 - */ - uint32_t blend_hb:14; - /** blend_vb : R/W; bitpos: [27:14]; default: 0; - * The vertical width of image block that would be filled in fix pixel filling mode or - * blend mode. The unit is pixel. Must be even num when YUV420 - */ - uint32_t blend_vb:14; - uint32_t reserved_28:4; - }; - uint32_t val; -} ppa_blend_tx_size_reg_t; - -/** Type of blend_fix_alpha register - * Blending engine alpha override register - */ -typedef union { - struct { - /** blend0_rx_fix_alpha : R/W; bitpos: [7:0]; default: 128; - * The value would replace the alpha value in received pixel for background plane of - * blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. - */ - uint32_t blend0_rx_fix_alpha:8; - /** blend1_rx_fix_alpha : R/W; bitpos: [15:8]; default: 128; - * The value would replace the alpha value in received pixel for foreground plane of - * blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. - */ - uint32_t blend1_rx_fix_alpha:8; - /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. - */ - uint32_t blend0_rx_alpha_mod:2; - /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. - */ - uint32_t blend1_rx_alpha_mod:2; - /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0; - * Set this bit to invert the original alpha value. When RX color mode is - * RGB565/RGB88. The original alpha value is 255. - */ - uint32_t blend0_rx_alpha_inv:1; - /** blend1_rx_alpha_inv : R/W; bitpos: [21]; default: 0; - * Set this bit to invert the original alpha value. When RX color mode is - * RGB565/RGB88. The original alpha value is 255. - */ - uint32_t blend1_rx_alpha_inv:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} ppa_blend_fix_alpha_reg_t; - -/** Type of blend_rgb register - * RGB color register - */ -typedef union { - struct { - /** blend1_rx_b : R/W; bitpos: [7:0]; default: 128; - * blue color for A4/A8 mode. - */ - uint32_t blend1_rx_b:8; - /** blend1_rx_g : R/W; bitpos: [15:8]; default: 128; - * green color for A4/A8 mode. - */ - uint32_t blend1_rx_g:8; - /** blend1_rx_r : R/W; bitpos: [23:16]; default: 128; - * red color for A4/A8 mode. - */ - uint32_t blend1_rx_r:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_blend_rgb_reg_t; - -/** Type of blend_fix_pixel register - * Blending engine fix pixel register - */ -typedef union { - struct { - /** blend_tx_fix_pixel : R/W; bitpos: [31:0]; default: 0; - * The configure fix pixel in fix pixel filling mode for blender engine. - */ - uint32_t blend_tx_fix_pixel:32; - }; - uint32_t val; -} ppa_blend_fix_pixel_reg_t; - -/** Type of ck_fg_low register - * foreground color key lower threshold - */ -typedef union { - struct { - /** colorkey_fg_b_low : R/W; bitpos: [7:0]; default: 255; - * color key lower threshold of foreground b channel - */ - uint32_t colorkey_fg_b_low:8; - /** colorkey_fg_g_low : R/W; bitpos: [15:8]; default: 255; - * color key lower threshold of foreground g channel - */ - uint32_t colorkey_fg_g_low:8; - /** colorkey_fg_r_low : R/W; bitpos: [23:16]; default: 255; - * color key lower threshold of foreground r channel - */ - uint32_t colorkey_fg_r_low:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_fg_low_reg_t; - -/** Type of ck_fg_high register - * foreground color key higher threshold - */ -typedef union { - struct { - /** colorkey_fg_b_high : R/W; bitpos: [7:0]; default: 0; - * color key higher threshold of foreground b channel - */ - uint32_t colorkey_fg_b_high:8; - /** colorkey_fg_g_high : R/W; bitpos: [15:8]; default: 0; - * color key higher threshold of foreground g channel - */ - uint32_t colorkey_fg_g_high:8; - /** colorkey_fg_r_high : R/W; bitpos: [23:16]; default: 0; - * color key higher threshold of foreground r channel - */ - uint32_t colorkey_fg_r_high:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_fg_high_reg_t; - -/** Type of ck_bg_low register - * background color key lower threshold - */ -typedef union { - struct { - /** colorkey_bg_b_low : R/W; bitpos: [7:0]; default: 255; - * color key lower threshold of background b channel - */ - uint32_t colorkey_bg_b_low:8; - /** colorkey_bg_g_low : R/W; bitpos: [15:8]; default: 255; - * color key lower threshold of background g channel - */ - uint32_t colorkey_bg_g_low:8; - /** colorkey_bg_r_low : R/W; bitpos: [23:16]; default: 255; - * color key lower threshold of background r channel - */ - uint32_t colorkey_bg_r_low:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_bg_low_reg_t; - -/** Type of ck_bg_high register - * background color key higher threshold - */ -typedef union { - struct { - /** colorkey_bg_b_high : R/W; bitpos: [7:0]; default: 0; - * color key higher threshold of background b channel - */ - uint32_t colorkey_bg_b_high:8; - /** colorkey_bg_g_high : R/W; bitpos: [15:8]; default: 0; - * color key higher threshold of background g channel - */ - uint32_t colorkey_bg_g_high:8; - /** colorkey_bg_r_high : R/W; bitpos: [23:16]; default: 0; - * color key higher threshold of background r channel - */ - uint32_t colorkey_bg_r_high:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_ck_bg_high_reg_t; - -/** Type of ck_default register - * default value when foreground and background both in color key range - */ -typedef union { - struct { - /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0; - * default B channel value of color key - */ - uint32_t colorkey_default_b:8; - /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0; - * default G channel value of color key - */ - uint32_t colorkey_default_g:8; - /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0; - * default R channel value of color key - */ - uint32_t colorkey_default_r:8; - /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0; - * when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the - * result is fg - */ - uint32_t colorkey_fg_bg_reverse:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} ppa_ck_default_reg_t; - -/** Type of sr_scal_rotate register - * Scaling and rotating coefficient register - */ -typedef union { - struct { - /** sr_scal_x_int : R/W; bitpos: [7:0]; default: 1; - * The integrated part of scaling coefficient in X direction. - */ - uint32_t sr_scal_x_int:8; - /** sr_scal_x_frag : R/W; bitpos: [11:8]; default: 0; - * The fragment part of scaling coefficient in X direction. - */ - uint32_t sr_scal_x_frag:4; - /** sr_scal_y_int : R/W; bitpos: [19:12]; default: 1; - * The integrated part of scaling coefficient in Y direction. - */ - uint32_t sr_scal_y_int:8; - /** sr_scal_y_frag : R/W; bitpos: [23:20]; default: 0; - * The fragment part of scaling coefficient in Y direction. - */ - uint32_t sr_scal_y_frag:4; - /** sr_rotate_angle : R/W; bitpos: [25:24]; default: 0; - * The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. - */ - uint32_t sr_rotate_angle:2; - /** scal_rotate_rst : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset scaling and rotating engine. - */ - uint32_t scal_rotate_rst:1; - /** scal_rotate_start : WT; bitpos: [27]; default: 0; - * Write 1 to enable scaling and rotating engine after parameter is configured. - */ - uint32_t scal_rotate_start:1; - /** sr_mirror_x : R/W; bitpos: [28]; default: 0; - * Image mirror in X direction. 0: disable, 1: enable - */ - uint32_t sr_mirror_x:1; - /** sr_mirror_y : R/W; bitpos: [29]; default: 0; - * Image mirror in Y direction. 0: disable, 1: enable - */ - uint32_t sr_mirror_y:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} ppa_sr_scal_rotate_reg_t; - -/** Type of sr_mem_pd register - * SR memory power done register - */ -typedef union { - struct { - /** sr_mem_clk_ena : R/W; bitpos: [0]; default: 0; - * Set this bit to force clock enable of scaling and rotating engine's data memory. - */ - uint32_t sr_mem_clk_ena:1; - /** sr_mem_force_pd : R/W; bitpos: [1]; default: 0; - * Set this bit to force power down scaling and rotating engine's data memory. - */ - uint32_t sr_mem_force_pd:1; - /** sr_mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force power up scaling and rotating engine's data memory. - */ - uint32_t sr_mem_force_pu:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} ppa_sr_mem_pd_reg_t; - -/** Type of reg_conf register - * Register clock enable register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * PPA register clock gate enable signal. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} ppa_reg_conf_reg_t; - -/** Type of eco_low register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0; - * Reserved. - */ - uint32_t rnd_eco_low:32; - }; - uint32_t val; -} ppa_eco_low_reg_t; - -/** Type of eco_high register - * Reserved. - */ -typedef union { - struct { - /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295; - * Reserved. - */ - uint32_t rnd_eco_high:32; - }; - uint32_t val; -} ppa_eco_high_reg_t; - -/** Type of sram_ctrl register - * PPA SRAM Control Register - */ -typedef union { - struct { - /** mem_aux_ctrl : R/W; bitpos: [13:0]; default: 4896; - * Control signals - */ - uint32_t mem_aux_ctrl:14; - uint32_t reserved_14:18; - }; - uint32_t val; -} ppa_sram_ctrl_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_raw register - * Raw status interrupt - */ -typedef union { - struct { - /** sr_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when scaling and rotating engine - * calculate one frame image. - */ - uint32_t sr_eof_int_raw:1; - /** blend_eof_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when blending engine calculate one frame - * image. - */ - uint32_t blend_eof_int_raw:1; - /** sr_param_cfg_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when the configured scaling and rotating - * coefficient is wrong. User can check the reasons through register - * PPA_SR_PARAM_ERR_ST_REG. - */ - uint32_t sr_param_cfg_err_int_raw:1; - /** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when the configured blending coefficient - * is wrong. User can check the reasons through register PPA_BLEND_ST_REG. - */ - uint32_t blend_param_cfg_err_int_raw:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_raw_reg_t; - -/** Type of int_st register - * Masked interrupt - */ -typedef union { - struct { - /** sr_eof_int_st : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. - */ - uint32_t sr_eof_int_st:1; - /** blend_eof_int_st : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. - */ - uint32_t blend_eof_int_st:1; - /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t sr_param_cfg_err_int_st:1; - /** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t blend_param_cfg_err_int_st:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_st_reg_t; - -/** Type of int_ena register - * Interrupt enable bits - */ -typedef union { - struct { - /** sr_eof_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the PPA_SR_EOF_INT interrupt. - */ - uint32_t sr_eof_int_ena:1; - /** blend_eof_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. - */ - uint32_t blend_eof_int_ena:1; - /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t sr_param_cfg_err_int_ena:1; - /** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t blend_param_cfg_err_int_ena:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_ena_reg_t; - -/** Type of int_clr register - * Interrupt clear bits - */ -typedef union { - struct { - /** sr_eof_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the PPA_SR_EOF_INT interrupt. - */ - uint32_t sr_eof_int_clr:1; - /** blend_eof_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the PPA_BLEND_EOF_INT interrupt. - */ - uint32_t blend_eof_int_clr:1; - /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. - */ - uint32_t sr_param_cfg_err_int_clr:1; - /** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. - */ - uint32_t blend_param_cfg_err_int_clr:1; - uint32_t reserved_4:28; - }; - uint32_t val; -} ppa_int_clr_reg_t; - - -/** Group: Status Registers */ -/** Type of clut_cnt register - * BLEND CLUT write counter register - */ -typedef union { - struct { - /** blend0_clut_cnt : RO; bitpos: [8:0]; default: 0; - * The write data counter of BLEND0 CLUT in fifo mode. - */ - uint32_t blend0_clut_cnt:9; - /** blend1_clut_cnt : RO; bitpos: [17:9]; default: 0; - * The write data counter of BLEND1 CLUT in fifo mode. - */ - uint32_t blend1_clut_cnt:9; - uint32_t reserved_18:14; - }; - uint32_t val; -} ppa_clut_cnt_reg_t; - -/** Type of blend_st register - * Blending engine status register - */ -typedef union { - struct { - /** blend_size_diff_st : RO; bitpos: [0]; default: 0; - * 1: indicate the size of two image is different. - */ - uint32_t blend_size_diff_st:1; - /** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0; - * Represents that x param is an odd num when enable yuv422 or yuv420 - */ - uint32_t blend_yuv_x_scale_err_st:1; - /** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0; - * Represents that y param is an odd num when enable yuv420 - */ - uint32_t blend_yuv_y_scale_err_st:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} ppa_blend_st_reg_t; - -/** Type of sr_param_err_st register - * Scaling and rotating coefficient error register - */ -typedef union { - struct { - /** tx_dscr_vb_err_st : RO; bitpos: [0]; default: 0; - * The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive - * descriptor is larger than VA in 2DDMA receive descriptor. - */ - uint32_t tx_dscr_vb_err_st:1; - /** tx_dscr_hb_err_st : RO; bitpos: [1]; default: 0; - * The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive - * descriptor is larger than HA in 2DDMA receive descriptor. - */ - uint32_t tx_dscr_hb_err_st:1; - /** y_rx_scal_equal_0_err_st : RO; bitpos: [2]; default: 0; - * The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. - */ - uint32_t y_rx_scal_equal_0_err_st:1; - /** rx_dscr_vb_err_st : RO; bitpos: [3]; default: 0; - * The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in - * 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor - */ - uint32_t rx_dscr_vb_err_st:1; - /** ydst_len_too_samll_err_st : RO; bitpos: [4]; default: 0; - * The error is that the scaled image width is 0. For example. when source width is - * 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as - * the result would be floored. - */ - uint32_t ydst_len_too_samll_err_st:1; - /** ydst_len_too_large_err_st : RO; bitpos: [5]; default: 0; - * The error is that the scaled width is larger than (2^13 - 1). - */ - uint32_t ydst_len_too_large_err_st:1; - /** x_rx_scal_equal_0_err_st : RO; bitpos: [6]; default: 0; - * The error is that the scaled image height is 0. - */ - uint32_t x_rx_scal_equal_0_err_st:1; - /** rx_dscr_hb_err_st : RO; bitpos: [7]; default: 0; - * The error is that the HB in 2DDMA transmit descriptor plus the offset of X - * coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit - * descriptor. - */ - uint32_t rx_dscr_hb_err_st:1; - /** xdst_len_too_samll_err_st : RO; bitpos: [8]; default: 0; - * The error is that the scaled image height is 0. For example. when source height is - * 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as - * the result would be floored. - */ - uint32_t xdst_len_too_samll_err_st:1; - /** xdst_len_too_large_err_st : RO; bitpos: [9]; default: 0; - * The error is that the scaled image height is larger than (2^13 - 1). - */ - uint32_t xdst_len_too_large_err_st:1; - /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0; - * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv422 or yuv420 rx - */ - uint32_t x_yuv420_rx_scale_err_st:1; - /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0; - * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable - * yuv420 rx - */ - uint32_t y_yuv420_rx_scale_err_st:1; - /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0; - * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv422 or yuv420 tx - */ - uint32_t x_yuv420_tx_scale_err_st:1; - /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0; - * The error is that the va/vb/y param in dma2d descriptor is an odd num when enable - * yuv420 tx - */ - uint32_t y_yuv420_tx_scale_err_st:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} ppa_sr_param_err_st_reg_t; - -/** Type of sr_status register - * SR FSM register - */ -typedef union { - struct { - /** sr_rx_dscr_sample_state : RO; bitpos: [1:0]; default: 0; - * Reserved. - */ - uint32_t sr_rx_dscr_sample_state:2; - /** sr_rx_scan_state : RO; bitpos: [3:2]; default: 0; - * Reserved. - */ - uint32_t sr_rx_scan_state:2; - /** sr_tx_dscr_sample_state : RO; bitpos: [5:4]; default: 0; - * Reserved. - */ - uint32_t sr_tx_dscr_sample_state:2; - /** sr_tx_scan_state : RO; bitpos: [8:6]; default: 0; - * Reserved. - */ - uint32_t sr_tx_scan_state:3; - uint32_t reserved_9:23; - }; - uint32_t val; -} ppa_sr_status_reg_t; - -/** Type of eco_cell_ctrl register - * Reserved. - */ -typedef union { - struct { - /** rdn_result : RO; bitpos: [0]; default: 0; - * Reserved. - */ - uint32_t rdn_result:1; - /** rdn_ena : R/W; bitpos: [1]; default: 0; - * Reserved. - */ - uint32_t rdn_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} ppa_eco_cell_ctrl_reg_t; - - -/** Group: Debug Register */ -/** Type of debug_ctrl0 register - * debug register - */ -typedef union { - struct { - /** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0; - * Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx - * bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6: - * blend output - */ - uint32_t dbg_replace_sel:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} ppa_debug_ctrl0_reg_t; - -/** Type of debug_ctrl1 register - * debug register - */ -typedef union { - struct { - /** dbg_replace_data : R/W; bitpos: [31:0]; default: 0; - * Configures the replace data - */ - uint32_t dbg_replace_data:32; - }; - uint32_t val; -} ppa_debug_ctrl1_reg_t; - - -/** Group: Configuration Register */ -/** Type of rgb2gray register - * rgb2gray register - */ -typedef union { - struct { - /** rgb2gray_b : R/W; bitpos: [7:0]; default: 85; - * Configures the b parameter for rgb2gray - */ - uint32_t rgb2gray_b:8; - /** rgb2gray_g : R/W; bitpos: [15:8]; default: 86; - * Configures the g parameter for rgb2gray - */ - uint32_t rgb2gray_g:8; - /** rgb2gray_r : R/W; bitpos: [23:16]; default: 85; - * Configures the r parameter for rgb2gray - */ - uint32_t rgb2gray_r:8; - uint32_t reserved_24:8; - }; - uint32_t val; -} ppa_rgb2gray_reg_t; - - -/** Group: Version Register */ -/** Type of date register - * PPA Version register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 539234848; - * register version. - */ - uint32_t date:32; - }; - uint32_t val; -} ppa_date_reg_t; - - -typedef struct ppa_dev_t { - volatile ppa_blend0_clut_data_reg_t blend0_clut_data; - volatile ppa_blend1_clut_data_reg_t blend1_clut_data; - uint32_t reserved_008; - volatile ppa_clut_conf_reg_t clut_conf; - volatile ppa_int_raw_reg_t int_raw; - volatile ppa_int_st_reg_t int_st; - volatile ppa_int_ena_reg_t int_ena; - volatile ppa_int_clr_reg_t int_clr; - volatile ppa_sr_color_mode_reg_t sr_color_mode; - volatile ppa_blend_color_mode_reg_t blend_color_mode; - volatile ppa_sr_byte_order_reg_t sr_byte_order; - volatile ppa_blend_byte_order_reg_t blend_byte_order; - uint32_t reserved_030; - volatile ppa_blend_trans_mode_reg_t blend_trans_mode; - volatile ppa_sr_fix_alpha_reg_t sr_fix_alpha; - volatile ppa_blend_tx_size_reg_t blend_tx_size; - volatile ppa_blend_fix_alpha_reg_t blend_fix_alpha; - uint32_t reserved_044; - volatile ppa_blend_rgb_reg_t blend_rgb; - volatile ppa_blend_fix_pixel_reg_t blend_fix_pixel; - volatile ppa_ck_fg_low_reg_t ck_fg_low; - volatile ppa_ck_fg_high_reg_t ck_fg_high; - volatile ppa_ck_bg_low_reg_t ck_bg_low; - volatile ppa_ck_bg_high_reg_t ck_bg_high; - volatile ppa_ck_default_reg_t ck_default; - volatile ppa_sr_scal_rotate_reg_t sr_scal_rotate; - volatile ppa_sr_mem_pd_reg_t sr_mem_pd; - volatile ppa_reg_conf_reg_t reg_conf; - volatile ppa_clut_cnt_reg_t clut_cnt; - volatile ppa_blend_st_reg_t blend_st; - volatile ppa_sr_param_err_st_reg_t sr_param_err_st; - volatile ppa_sr_status_reg_t sr_status; - volatile ppa_eco_low_reg_t eco_low; - volatile ppa_eco_high_reg_t eco_high; - volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl; - volatile ppa_sram_ctrl_reg_t sram_ctrl; - volatile ppa_debug_ctrl0_reg_t debug_ctrl0; - volatile ppa_debug_ctrl1_reg_t debug_ctrl1; - volatile ppa_rgb2gray_reg_t rgb2gray; - uint32_t reserved_09c[25]; - volatile ppa_date_reg_t date; -} ppa_dev_t; - -extern ppa_dev_t PPA; - -#ifndef __cplusplus -_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h index f843b5b49d..baa0dbb88d 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h @@ -43,10 +43,9 @@ extern "C" { #define PPA_CLUT_CONF_REG (DR_REG_PPA_BASE + 0xc) /** PPA_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; * 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register - * PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: - * memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr - * should be 01 to access sr clut and should be 10 to access blend0 clut and should be - * 11 to access blend 1 clut in memory mode. + * PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: + * memory mode to wr/rd blend0/blend1 clut RAM. The bit 11 and 10 of the waddr + * should be 01 to access blend0 clut and should be 10 to access blend1 clut in memory mode. */ #define PPA_APB_FIFO_MASK (BIT(0)) #define PPA_APB_FIFO_MASK_M (PPA_APB_FIFO_MASK_V << PPA_APB_FIFO_MASK_S) @@ -225,7 +224,7 @@ extern "C" { #define PPA_BLEND_EOF_INT_CLR_V 0x00000001U #define PPA_BLEND_EOF_INT_CLR_S 1 /** PPA_SR_PARAM_CFG_ERR_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ #define PPA_SR_PARAM_CFG_ERR_INT_CLR (BIT(2)) #define PPA_SR_PARAM_CFG_ERR_INT_CLR_M (PPA_SR_PARAM_CFG_ERR_INT_CLR_V << PPA_SR_PARAM_CFG_ERR_INT_CLR_S) @@ -273,20 +272,20 @@ extern "C" { #define PPA_YUV_TX_RANGE_M (PPA_YUV_TX_RANGE_V << PPA_YUV_TX_RANGE_S) #define PPA_YUV_TX_RANGE_V 0x00000001U #define PPA_YUV_TX_RANGE_S 9 -/** PPA_YUV2RGB_PROTOCAL : R/W; bitpos: [10]; default: 0; +/** PPA_YUV2RGB_PROTOCOL : R/W; bitpos: [10]; default: 0; * YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 */ -#define PPA_YUV2RGB_PROTOCAL (BIT(10)) -#define PPA_YUV2RGB_PROTOCAL_M (PPA_YUV2RGB_PROTOCAL_V << PPA_YUV2RGB_PROTOCAL_S) -#define PPA_YUV2RGB_PROTOCAL_V 0x00000001U -#define PPA_YUV2RGB_PROTOCAL_S 10 -/** PPA_RGB2YUV_PROTOCAL : R/W; bitpos: [11]; default: 0; +#define PPA_YUV2RGB_PROTOCOL (BIT(10)) +#define PPA_YUV2RGB_PROTOCOL_M (PPA_YUV2RGB_PROTOCOL_V << PPA_YUV2RGB_PROTOCOL_S) +#define PPA_YUV2RGB_PROTOCOL_V 0x00000001U +#define PPA_YUV2RGB_PROTOCOL_S 10 +/** PPA_RGB2YUV_PROTOCOL : R/W; bitpos: [11]; default: 0; * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 */ -#define PPA_RGB2YUV_PROTOCAL (BIT(11)) -#define PPA_RGB2YUV_PROTOCAL_M (PPA_RGB2YUV_PROTOCAL_V << PPA_RGB2YUV_PROTOCAL_S) -#define PPA_RGB2YUV_PROTOCAL_V 0x00000001U -#define PPA_RGB2YUV_PROTOCAL_S 11 +#define PPA_RGB2YUV_PROTOCOL (BIT(11)) +#define PPA_RGB2YUV_PROTOCOL_M (PPA_RGB2YUV_PROTOCOL_V << PPA_RGB2YUV_PROTOCOL_S) +#define PPA_RGB2YUV_PROTOCOL_V 0x00000001U +#define PPA_RGB2YUV_PROTOCOL_S 11 /** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0; * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY */ @@ -337,20 +336,20 @@ extern "C" { #define PPA_BLEND_TX_YUV_RANGE_M (PPA_BLEND_TX_YUV_RANGE_V << PPA_BLEND_TX_YUV_RANGE_S) #define PPA_BLEND_TX_YUV_RANGE_V 0x00000001U #define PPA_BLEND_TX_YUV_RANGE_S 13 -/** PPA_BLEND0_RX_YUV2RGB_PROTOCAL : R/W; bitpos: [14]; default: 0; +/** PPA_BLEND0_RX_YUV2RGB_PROTOCOL : R/W; bitpos: [14]; default: 0; * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 */ -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL (BIT(14)) -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S) -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V 0x00000001U -#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S 14 -/** PPA_BLEND_TX_RGB2YUV_PROTOCAL : R/W; bitpos: [15]; default: 0; +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL (BIT(14)) +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S) +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V 0x00000001U +#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S 14 +/** PPA_BLEND_TX_RGB2YUV_PROTOCOL : R/W; bitpos: [15]; default: 0; * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 */ -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL (BIT(15)) -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_M (PPA_BLEND_TX_RGB2YUV_PROTOCAL_V << PPA_BLEND_TX_RGB2YUV_PROTOCAL_S) -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_V 0x00000001U -#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_S 15 +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL (BIT(15)) +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_M (PPA_BLEND_TX_RGB2YUV_PROTOCOL_V << PPA_BLEND_TX_RGB2YUV_PROTOCOL_S) +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_V 0x00000001U +#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_S 15 /** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0; * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY */ @@ -554,7 +553,7 @@ extern "C" { #define PPA_BLEND1_RX_FIX_ALPHA_S 8 /** PPA_BLEND0_RX_ALPHA_MOD : R/W; bitpos: [17:16]; default: 0; * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Original alpha multiply with PPA_SR_BLEND0_ALPHA/256. */ #define PPA_BLEND0_RX_ALPHA_MOD 0x00000003U #define PPA_BLEND0_RX_ALPHA_MOD_M (PPA_BLEND0_RX_ALPHA_MOD_V << PPA_BLEND0_RX_ALPHA_MOD_S) @@ -562,7 +561,7 @@ extern "C" { #define PPA_BLEND0_RX_ALPHA_MOD_S 16 /** PPA_BLEND1_RX_ALPHA_MOD : R/W; bitpos: [19:18]; default: 0; * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Original alpha multiply with PPA_SR_BLEND1_ALPHA/256. */ #define PPA_BLEND1_RX_ALPHA_MOD 0x00000003U #define PPA_BLEND1_RX_ALPHA_MOD_M (PPA_BLEND1_RX_ALPHA_MOD_V << PPA_BLEND1_RX_ALPHA_MOD_S) diff --git a/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h index fe85942a62..855a9df1e9 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h @@ -91,12 +91,12 @@ typedef union { struct { /** sr_rx_cm : R/W; bitpos: [3:0]; default: 0; * The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: - * RGB888. 2: RGB565. 8: YUV420. others: Reserved. + * RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. */ uint32_t sr_rx_cm:4; /** sr_tx_cm : R/W; bitpos: [7:4]; default: 0; * The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. - * 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + * 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved. */ uint32_t sr_tx_cm:4; /** yuv_rx_range : R/W; bitpos: [8]; default: 0; @@ -115,7 +115,11 @@ typedef union { * RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 */ uint32_t rgb2yuv_protocol:1; - uint32_t reserved_12:20; + /** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + */ + uint32_t yuv422_rx_byte_order:2; + uint32_t reserved_14:18; }; uint32_t val; } ppa_sr_color_mode_reg_t; @@ -127,7 +131,7 @@ typedef union { struct { /** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0; * The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved. 4: L8. 5: L4. + * RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY */ uint32_t blend0_rx_cm:4; /** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0; @@ -137,10 +141,30 @@ typedef union { uint32_t blend1_rx_cm:4; /** blend_tx_cm : R/W; bitpos: [11:8]; default: 0; * The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: - * RGB565. 3: Reserved.. + * RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY */ uint32_t blend_tx_cm:4; - uint32_t reserved_12:20; + /** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0; + * YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range + */ + uint32_t blend0_rx_yuv_range:1; + /** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0; + * YUV output range when blend tx cm is yuv. 0: limit range. 1: full range + */ + uint32_t blend_tx_yuv_range:1; + /** blend0_rx_yuv2rgb_protocol : R/W; bitpos: [14]; default: 0; + * YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709 + */ + uint32_t blend0_rx_yuv2rgb_protocol:1; + /** blend_tx_rgb2yuv_protocol : R/W; bitpos: [15]; default: 0; + * RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709 + */ + uint32_t blend_tx_rgb2yuv_protocol:1; + /** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0; + * YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY + */ + uint32_t blend0_rx_yuv422_byte_order:2; + uint32_t reserved_18:14; }; uint32_t val; } ppa_blend_color_mode_reg_t; @@ -165,7 +189,11 @@ typedef union { * to improve efficient accessing external memory. */ uint32_t sr_macro_bk_ro_bypass:1; - uint32_t reserved_3:29; + /** sr_bk_size_sel : R/W; bitpos: [3]; default: 0; + * sel srm pix_blk size, 0:32x32, 1:16x16 + */ + uint32_t sr_bk_size_sel:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_sr_byte_order_reg_t; @@ -227,7 +255,12 @@ typedef union { * write 1 then write 0 to reset blending engine. */ uint32_t blend_rst:1; - uint32_t reserved_5:27; + /** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0; + * unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and + * ls_enc + */ + uint32_t blend_tx_inf_sel:2; + uint32_t reserved_7:25; }; uint32_t val; } ppa_blend_trans_mode_reg_t; @@ -263,13 +296,13 @@ typedef union { typedef union { struct { /** blend_hb : R/W; bitpos: [13:0]; default: 0; - * The horizontal width of image block that would be filled in fix pixel filling mode. - * The unit is pixel + * The horizontal width of image block that would be filled in fix pixel filling mode + * or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420 */ uint32_t blend_hb:14; /** blend_vb : R/W; bitpos: [27:14]; default: 0; - * The vertical width of image block that would be filled in fix pixel filling mode. - * The unit is pixel + * The vertical width of image block that would be filled in fix pixel filling mode or + * blend mode. The unit is pixel. Must be even num when YUV420 */ uint32_t blend_vb:14; uint32_t reserved_28:4; @@ -293,13 +326,13 @@ typedef union { */ uint32_t blend1_rx_fix_alpha:8; /** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2: + * Original alpha multiply with PPA_BLEND0_FIX_ALPHA/256. */ uint32_t blend0_rx_alpha_mod:2; /** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0; - * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: - * Original alpha multiply with PPA_SR_FIX_ALPHA/256. + * Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2: + * Original alpha multiply with PPA_BLEND1_FIX_ALPHA/256. */ uint32_t blend1_rx_alpha_mod:2; /** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0; @@ -612,7 +645,12 @@ typedef union { * PPA_SR_PARAM_ERR_ST_REG. */ uint32_t sr_param_cfg_err_int_raw:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the configured blending coefficient + * is wrong. User can check the reasons through register PPA_BLEND_ST_REG. + */ + uint32_t blend_param_cfg_err_int_raw:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_raw_reg_t; @@ -631,10 +669,14 @@ typedef union { */ uint32_t blend_eof_int_st:1; /** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ uint32_t sr_param_cfg_err_int_st:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_st:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_st_reg_t; @@ -653,10 +695,14 @@ typedef union { */ uint32_t blend_eof_int_ena:1; /** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ uint32_t sr_param_cfg_err_int_ena:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_ena:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_ena_reg_t; @@ -675,10 +721,14 @@ typedef union { */ uint32_t blend_eof_int_clr:1; /** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + * Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt. */ uint32_t sr_param_cfg_err_int_clr:1; - uint32_t reserved_3:29; + /** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt. + */ + uint32_t blend_param_cfg_err_int_clr:1; + uint32_t reserved_4:28; }; uint32_t val; } ppa_int_clr_reg_t; @@ -712,7 +762,15 @@ typedef union { * 1: indicate the size of two image is different. */ uint32_t blend_size_diff_st:1; - uint32_t reserved_1:31; + /** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0; + * Represents that x param is an odd num when enable yuv422 or yuv420 + */ + uint32_t blend_yuv_x_scale_err_st:1; + /** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0; + * Represents that y param is an odd num when enable yuv420 + */ + uint32_t blend_yuv_y_scale_err_st:1; + uint32_t reserved_3:29; }; uint32_t val; } ppa_blend_st_reg_t; @@ -773,7 +831,7 @@ typedef union { uint32_t xdst_len_too_large_err_st:1; /** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0; * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv420 rx + * yuv422 or yuv420 rx */ uint32_t x_yuv420_rx_scale_err_st:1; /** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0; @@ -783,7 +841,7 @@ typedef union { uint32_t y_yuv420_rx_scale_err_st:1; /** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0; * The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable - * yuv420 tx + * yuv422 or yuv420 tx */ uint32_t x_yuv420_tx_scale_err_st:1; /** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0; @@ -841,13 +899,68 @@ typedef union { } ppa_eco_cell_ctrl_reg_t; +/** Group: Debug Register */ +/** Type of debug_ctrl0 register + * debug register + */ +typedef union { + struct { + /** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0; + * Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx + * bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6: + * blend output + */ + uint32_t dbg_replace_sel:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} ppa_debug_ctrl0_reg_t; + +/** Type of debug_ctrl1 register + * debug register + */ +typedef union { + struct { + /** dbg_replace_data : R/W; bitpos: [31:0]; default: 0; + * Configures the replace data + */ + uint32_t dbg_replace_data:32; + }; + uint32_t val; +} ppa_debug_ctrl1_reg_t; + + +/** Group: Configuration Register */ +/** Type of rgb2gray register + * rgb2gray register + */ +typedef union { + struct { + /** rgb2gray_b : R/W; bitpos: [7:0]; default: 85; + * Configures the b parameter for rgb2gray + */ + uint32_t rgb2gray_b:8; + /** rgb2gray_g : R/W; bitpos: [15:8]; default: 86; + * Configures the g parameter for rgb2gray + */ + uint32_t rgb2gray_g:8; + /** rgb2gray_r : R/W; bitpos: [23:16]; default: 85; + * Configures the r parameter for rgb2gray + */ + uint32_t rgb2gray_r:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} ppa_rgb2gray_reg_t; + + /** Group: Version Register */ /** Type of date register * PPA Version register */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 36716609; + /** date : R/W; bitpos: [31:0]; default: 539234848; * register version. */ uint32_t date:32; @@ -893,7 +1006,10 @@ typedef struct ppa_dev_t { volatile ppa_eco_high_reg_t eco_high; volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl; volatile ppa_sram_ctrl_reg_t sram_ctrl; - uint32_t reserved_090[28]; + volatile ppa_debug_ctrl0_reg_t debug_ctrl0; + volatile ppa_debug_ctrl1_reg_t debug_ctrl1; + volatile ppa_rgb2gray_reg_t rgb2gray; + uint32_t reserved_09c[25]; volatile ppa_date_reg_t date; } ppa_dev_t;