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feat(cache): supported cache on c61

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This commit is contained in:
Armando
2024-07-29 16:03:13 +08:00
parent b5ab82ce3c
commit 67b8dbb5e5
14 changed files with 96 additions and 33 deletions
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6
components/esp_mm/test_apps/mm/main/test_cache_msync.c
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@@ -40,6 +40,12 @@ const static char *TAG = "CACHE_TEST";
#elif CONFIG_IDF_TARGET_ESP32P4
#define TEST_SYNC_START (SOC_DRAM_PSRAM_ADDRESS_LOW + TEST_OFFSET)
#define TEST_SYNC_SIZE CONFIG_CACHE_L2_CACHE_SIZE
#elif CONFIG_IDF_TARGET_ESP32C5
#define TEST_SYNC_START (SOC_DRAM_PSRAM_ADDRESS_LOW + TEST_OFFSET)
#define TEST_SYNC_SIZE CONFIG_CACHE_L1_CACHE_SIZE
#elif CONFIG_IDF_TARGET_ESP32C61
#define TEST_SYNC_START (SOC_DRAM_PSRAM_ADDRESS_LOW + TEST_OFFSET)
#define TEST_SYNC_SIZE CONFIG_CACHE_L1_CACHE_SIZE
#endif
#define RECORD_TIME_PREPARE() uint32_t __t1, __t2