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refactor(spi_slave): replace dma_ll in slave hal layer (part 2.2)

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wanlei
2023-12-13 12:51:58 +08:00
committed by Wan Lei
parent 31f4e9c698
commit 67f798b666
15 changed files with 195 additions and 222 deletions
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12
components/hal/esp32c3/include/hal/spi_ll.h
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@@ -315,7 +315,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw)
/**
* Reset SPI CPU TX FIFO
*
* On ESP32C3, this function is not seperated
* On ESP32C3, this function is not separated
*
* @param hw Beginning address of the peripheral registers.
*/
@@ -328,7 +328,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
/**
* Reset SPI CPU RX FIFO
*
* On ESP32C3, this function is not seperated
* On ESP32C3, this function is not separated
*
* @param hw Beginning address of the peripheral registers.
*/
@@ -713,7 +713,7 @@ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_cl
* Get the frequency of given dividers. Don't use in app.
*
* @param fapb APB clock of the system.
* @param pre Pre devider.
* @param pre Pre divider.
* @param n Main divider.
*
* @return Frequency of given dividers.
@@ -724,10 +724,10 @@ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
}
/**
* Calculate the nearest frequency avaliable for master.
* Calculate the nearest frequency available for master.
*
* @param fapb APB clock of the system.
* @param hz Frequncy desired.
* @param hz Frequency desired.
* @param duty_cycle Duty cycle desired.
* @param out_reg Output address to store the calculated clock configurations for the return frequency.
*
@@ -807,7 +807,7 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_
*
* @param hw Beginning address of the peripheral registers.
* @param fapb APB clock of the system.
* @param hz Frequncy desired.
* @param hz Frequency desired.
* @param duty_cycle Duty cycle desired.
*
* @return Actual frequency that is used.