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Security: ESP32C3 memory protection feature (IRAM0/DRAM0)
Software support for PMS module. Allows controlled memory access to IRAM (R/W/X) and DRAM0 (R/W) On/locked by default, configurable in Kconfig (esp_system) Closes https://jira.espressif.com:8443/browse/IDF-2092
This commit is contained in:
Martin Vychodil
446
components/hal/esp32c3/include/hal/memprot_ll.h
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446
components/hal/esp32c3/include/hal/memprot_ll.h
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "soc/sensitive_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* === globals ====
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*/
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#ifndef SRAM_IRAM_START
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#define SRAM_IRAM_START 0x4037C000
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#endif
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#ifndef SRAM_DRAM_START
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#define SRAM_DRAM_START 0x3FC7C000
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#endif
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/* ICache size is fixed to 16KB on ESP32-C3 */
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#ifndef ICACHE_SIZE
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#define ICACHE_SIZE 0x4000
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#endif
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#ifndef I_D_SRAM_SEGMENT_SIZE
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#define I_D_SRAM_SEGMENT_SIZE 0x20000
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#endif
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#ifndef I_D_SRAM_OFFSET
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#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
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#endif
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/* 2nd stage bootloader iram_loader_seg start address */
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#ifndef SRAM_DRAM_END
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#define SRAM_DRAM_END (0x403D0000 - I_D_SRAM_OFFSET)
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#endif
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#ifndef SRAM_IRAM_ORG
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#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
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#endif
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#ifndef SRAM_DRAM_ORG
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#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE)
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#endif
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#ifndef I_D_SRAM_SIZE
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#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
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#endif
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#define I_D_SPLIT_LINE_SHIFT 0x9
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#define MAP_DRAM_TO_IRAM(addr) (addr - SRAM_DRAM_START + SRAM_IRAM_START)
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#define MAP_IRAM_TO_DRAM(addr) (addr - SRAM_IRAM_START + SRAM_DRAM_START)
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static inline void memprot_ll_set_iram0_dram0_split_line_lock(bool lock)
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{
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REG_WRITE(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG, lock ? 1 : 0);
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}
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static inline bool memprot_ll_get_iram0_dram0_split_line_lock(void)
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{
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return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1;
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}
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/**
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* === IRAM0 ====
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*/
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//16kB (CACHE)
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#define IRAM0_SRAM_LEVEL_0_LOW SRAM_IRAM_START //0x40370000
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#define IRAM0_SRAM_LEVEL_0_HIGH (IRAM0_SRAM_LEVEL_0_LOW + ICACHE_SIZE - 0x1) //0x4037FFFF
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//128kB (LEVEL 1)
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#define IRAM0_SRAM_LEVEL_1_LOW (IRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x40380000
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#define IRAM0_SRAM_LEVEL_1_HIGH (IRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x4039FFFF
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//128kB (LEVEL 2)
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#define IRAM0_SRAM_LEVEL_2_LOW (IRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x403A0000
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#define IRAM0_SRAM_LEVEL_2_HIGH (IRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403BFFFF
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//128kB (LEVEL 3)
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#define IRAM0_SRAM_LEVEL_3_LOW (IRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x403C0000
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#define IRAM0_SRAM_LEVEL_3_HIGH (IRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x403DFFFF
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//permission bits
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R 0x1
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W 0x2
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#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F 0x4
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static inline uint32_t memprot_ll_iram0_get_intr_source_num(void)
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{
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return ETS_CORE0_IRAM0_PMS_INTR_SOURCE;
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}
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/* SPLIT LINE */
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static inline void memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg)
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{
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uint32_t addr = (uint32_t)line_addr;
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assert( addr >= IRAM0_SRAM_LEVEL_1_LOW && addr <= IRAM0_SRAM_LEVEL_3_HIGH );
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uint32_t category[3] = {0};
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if (addr <= IRAM0_SRAM_LEVEL_1_HIGH) {
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category[0] = 0x2;
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category[1] = category[2] = 0x3;
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} else if (addr >= IRAM0_SRAM_LEVEL_2_LOW && addr <= IRAM0_SRAM_LEVEL_2_HIGH) {
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category[1] = 0x2;
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category[2] = 0x3;
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} else {
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category[2] = 0x2;
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}
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//category bits are the same for all areas
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uint32_t category_bits =
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(category[0] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S) |
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(category[1] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S) |
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(category[2] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S);
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uint32_t conf_addr = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S;
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uint32_t reg_cfg = conf_addr | category_bits;
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REG_WRITE(sensitive_reg, reg_cfg);
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}
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/* can be both IRAM0/DRAM0 address */
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static inline void memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr)
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{
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memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG);
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}
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static inline void memprot_ll_set_iram0_split_line_I_0(const void *line_addr)
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{
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memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG);
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}
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static inline void memprot_ll_set_iram0_split_line_I_1(const void *line_addr)
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{
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memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG);
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}
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/* PMS */
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static inline void memprot_ll_iram0_set_pms_lock(bool lock)
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{
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REG_WRITE(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG, lock ? 1 : 0);
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}
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static inline bool memprot_ll_iram0_get_pms_lock(void)
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{
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return REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1;
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}
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//world_0 permissions
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static inline uint32_t memprot_ll_iram0_set_permissions(bool r, bool w, bool x)
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{
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uint32_t permissions = 0;
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if ( r ) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R;
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}
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if ( w ) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W;
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}
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if ( x ) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_F;
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}
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return permissions;
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}
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static inline void memprot_ll_iram0_set_pms_area_0(bool r, bool w, bool x)
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{
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REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0, memprot_ll_iram0_set_permissions(r, w, x));
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}
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static inline void memprot_ll_iram0_set_pms_area_1(bool r, bool w, bool x)
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{
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REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1, memprot_ll_iram0_set_permissions(r, w, x));
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}
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static inline void memprot_ll_iram0_set_pms_area_2(bool r, bool w, bool x)
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{
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REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2, memprot_ll_iram0_set_permissions(r, w, x));
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}
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static inline void memprot_ll_iram0_set_pms_area_3(bool r, bool w, bool x)
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{
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REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3, memprot_ll_iram0_set_permissions(r, w, x));
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}
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/* MONITOR */
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static inline void memprot_ll_iram0_set_monitor_lock(bool lock)
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{
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REG_WRITE(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG, lock ? 1 : 0);
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}
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static inline bool memprot_ll_iram0_get_monitor_lock(void)
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{
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return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1;
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}
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static inline void memprot_ll_iram0_set_monitor_en(bool enable)
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{
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if ( enable ) {
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REG_SET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN );
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} else {
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REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN );
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}
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}
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static inline bool memprot_ll_iram0_get_monitor_en(void)
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{
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return REG_GET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN ) == 1;
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}
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static inline void memprot_ll_iram0_clear_monitor_intr(void)
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{
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REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR );
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}
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static inline uint32_t memprot_ll_iram0_get_monitor_status_intr(void)
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{
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return REG_GET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR );
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}
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static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_wr(void)
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{
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return REG_GET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR );
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}
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static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_loadstore(void)
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{
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return REG_GET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE );
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}
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static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_world(void)
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{
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return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD );
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}
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static inline uint32_t memprot_ll_iram0_get_monitor_status_fault_addr(void)
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{
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return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR );
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}
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/**
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* === DRAM0 ====
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*/
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//cache not available from DRAM
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#define DRAM0_SRAM_LEVEL_0_LOW SRAM_DRAM_START //0x3FC7C000
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#define DRAM0_SRAM_LEVEL_0_HIGH (DRAM0_SRAM_LEVEL_0_LOW + ICACHE_SIZE - 0x1) //0x3FC7FFFF
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//128kB
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#define DRAM0_SRAM_LEVEL_1_LOW (DRAM0_SRAM_LEVEL_0_HIGH + 0x1) //0x3FC80000
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#define DRAM0_SRAM_LEVEL_1_HIGH (DRAM0_SRAM_LEVEL_1_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FC9FFFF
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//128kB
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#define DRAM0_SRAM_LEVEL_2_LOW (DRAM0_SRAM_LEVEL_1_HIGH + 0x1) //0x3FCA0000
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#define DRAM0_SRAM_LEVEL_2_HIGH (DRAM0_SRAM_LEVEL_2_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCBFFFF
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//128kB
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#define DRAM0_SRAM_LEVEL_3_LOW (DRAM0_SRAM_LEVEL_2_HIGH + 0x1) //0x3FCC0000
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#define DRAM0_SRAM_LEVEL_3_HIGH (DRAM0_SRAM_LEVEL_3_LOW + I_D_SRAM_SEGMENT_SIZE - 0x1) //0x3FCDFFFF
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#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W 0x2
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#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R 0x1
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static inline uint32_t memprot_ll_dram0_get_intr_source_num(void)
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{
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return ETS_CORE0_DRAM0_PMS_INTR_SOURCE;
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}
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/* SPLIT LINE */
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static inline void memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg)
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{
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uint32_t addr = (uint32_t)line_addr;
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assert( addr >= DRAM0_SRAM_LEVEL_1_LOW && addr <= DRAM0_SRAM_LEVEL_3_HIGH );
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uint32_t category[3] = {0};
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if (addr <= DRAM0_SRAM_LEVEL_1_HIGH) {
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category[0] = 0x2;
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category[1] = category[2] = 0x3;
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} else if (addr >= DRAM0_SRAM_LEVEL_2_LOW && addr <= DRAM0_SRAM_LEVEL_2_HIGH) {
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category[1] = 0x2;
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category[2] = 0x3;
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} else {
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category[2] = 0x2;
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}
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//category bits are the same for all areas
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uint32_t category_bits =
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(category[0] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S) |
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(category[1] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S) |
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(category[2] << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S);
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uint32_t conf_addr = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S;
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uint32_t reg_cfg = conf_addr | category_bits;
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REG_WRITE(sensitive_reg, reg_cfg);
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}
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static inline void memprot_ll_set_dram0_split_line_D_0(const void *line_addr)
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{
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memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG);
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}
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static inline void memprot_ll_set_dram0_split_line_D_1(const void *line_addr)
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{
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memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG);
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}
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/* PMS */
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static inline void memprot_ll_dram0_set_pms_lock(bool lock)
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{
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REG_WRITE(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG, lock ? 1 : 0);
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}
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static inline bool memprot_ll_dram0_get_pms_lock(void)
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{
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return REG_READ(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG) == 1;
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}
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static inline uint32_t memprot_ll_dram0_set_permissions(bool r, bool w)
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{
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uint32_t permissions = 0;
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if ( r ) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_R;
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}
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if ( w ) {
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permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_W;
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}
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return permissions;
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}
|
||||
|
||||
static inline void memprot_ll_dram0_set_pms_area_0(bool r, bool w)
|
||||
{
|
||||
REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0, memprot_ll_dram0_set_permissions(r, w));
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_set_pms_area_1(bool r, bool w)
|
||||
{
|
||||
REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1, memprot_ll_dram0_set_permissions(r, w));
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_set_pms_area_2(bool r, bool w)
|
||||
{
|
||||
REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2, memprot_ll_dram0_set_permissions(r, w));
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_set_pms_area_3(bool r, bool w)
|
||||
{
|
||||
REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3, memprot_ll_dram0_set_permissions(r, w));
|
||||
}
|
||||
|
||||
|
||||
/* MONITOR */
|
||||
|
||||
static inline void memprot_ll_dram0_set_monitor_lock(bool lock)
|
||||
{
|
||||
REG_WRITE(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG, lock ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline bool memprot_ll_dram0_get_monitor_lock(void)
|
||||
{
|
||||
return REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG) == 1;
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_set_monitor_en(bool enable)
|
||||
{
|
||||
if ( enable ) {
|
||||
REG_SET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN );
|
||||
} else {
|
||||
REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN );
|
||||
}
|
||||
}
|
||||
|
||||
static inline bool memprot_ll_dram0_get_monitor_en(void)
|
||||
{
|
||||
return REG_GET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN ) == 1;
|
||||
}
|
||||
|
||||
static inline void memprot_ll_dram0_clear_monitor_intr(void)
|
||||
{
|
||||
REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR );
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_intr(void)
|
||||
{
|
||||
return REG_GET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR );
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_lock(void)
|
||||
{
|
||||
return REG_GET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK );
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_world(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD );
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_addr(void)
|
||||
{
|
||||
return REG_GET_FIELD( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR );
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_wr(void)
|
||||
{
|
||||
return REG_GET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR );
|
||||
}
|
||||
|
||||
static inline uint32_t memprot_ll_dram0_get_monitor_status_fault_byte_en(void)
|
||||
{
|
||||
return REG_GET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN );
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user