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feat(pmu): support ldo dbias & ocode read from efuse for chip752mp
This commit is contained in:
hongshuqing
committed by
chaijie@espressif.com
chaijie@espressif.com
parent
0c76f6c556
commit
6a7191b2d9
@@ -834,33 +834,88 @@ extern "C" {
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* Represents rd_mac_sys
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*/
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#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50)
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/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
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* Reserved.
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* This field is only for internal debugging purposes. Do not use it in applications.
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/** EFUSE_TRIM_N_BIAS : R; bitpos: [4:0]; default: 0;
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* PADC CAL N bias
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*/
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#define EFUSE_MAC_RESERVED_2 0x0003FFFFU
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#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
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#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU
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#define EFUSE_MAC_RESERVED_2_S 0
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/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
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* Represents the first 14-bit of zeroth part of system data.
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#define EFUSE_TRIM_N_BIAS 0x0000001FU
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#define EFUSE_TRIM_N_BIAS_M (EFUSE_TRIM_N_BIAS_V << EFUSE_TRIM_N_BIAS_S)
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#define EFUSE_TRIM_N_BIAS_V 0x0000001FU
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#define EFUSE_TRIM_N_BIAS_S 0
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/** EFUSE_TRIM_P_BIAS : R; bitpos: [9:5]; default: 0;
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* PADC CAL P bias
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*/
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#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU
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#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
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#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU
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#define EFUSE_SYS_DATA_PART0_0_S 18
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#define EFUSE_TRIM_P_BIAS 0x0000001FU
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#define EFUSE_TRIM_P_BIAS_M (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S)
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#define EFUSE_TRIM_P_BIAS_V 0x0000001FU
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#define EFUSE_TRIM_P_BIAS_S 5
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/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [13:10]; default: 0;
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* Active HP DBIAS of fixed voltage
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*/
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#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU
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#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
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#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU
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#define EFUSE_ACTIVE_HP_DBIAS_S 10
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/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [17:14]; default: 0;
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* Active LP DBIAS of fixed voltage
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*/
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#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU
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#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
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#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU
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#define EFUSE_ACTIVE_LP_DBIAS_S 14
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/** EFUSE_LSLP_HP_DBG : R; bitpos: [19:18]; default: 0;
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* LSLP HP DBG of fixed voltage
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*/
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#define EFUSE_LSLP_HP_DBG 0x00000003U
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#define EFUSE_LSLP_HP_DBG_M (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S)
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#define EFUSE_LSLP_HP_DBG_V 0x00000003U
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#define EFUSE_LSLP_HP_DBG_S 18
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/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [23:20]; default: 0;
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* LSLP HP DBIAS of fixed voltage
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*/
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#define EFUSE_LSLP_HP_DBIAS 0x0000000FU
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#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
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#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU
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#define EFUSE_LSLP_HP_DBIAS_S 20
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/** EFUSE_DSLP_LP_DBG : R; bitpos: [27:24]; default: 0;
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* DSLP LP DBG of fixed voltage
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*/
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#define EFUSE_DSLP_LP_DBG 0x0000000FU
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#define EFUSE_DSLP_LP_DBG_M (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S)
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#define EFUSE_DSLP_LP_DBG_V 0x0000000FU
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#define EFUSE_DSLP_LP_DBG_S 24
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/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [31:28]; default: 0;
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* DSLP LP DBIAS of fixed voltage
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*/
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#define EFUSE_DSLP_LP_DBIAS 0x0000000FU
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#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
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#define EFUSE_DSLP_LP_DBIAS_V 0x0000000FU
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#define EFUSE_DSLP_LP_DBIAS_S 28
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/** EFUSE_RD_MAC_SYS4_REG register
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* Represents rd_mac_sys
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*/
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#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54)
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/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
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* Represents the second 32-bit of zeroth part of system data.
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/** EFUSE_DSLP_LP_DBIAS_1 : R; bitpos: [0]; default: 0;
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* DSLP LP DBIAS of fixed voltage
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*/
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#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
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#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART0_1_S 0
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#define EFUSE_DSLP_LP_DBIAS_1 (BIT(0))
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#define EFUSE_DSLP_LP_DBIAS_1_M (EFUSE_DSLP_LP_DBIAS_1_V << EFUSE_DSLP_LP_DBIAS_1_S)
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#define EFUSE_DSLP_LP_DBIAS_1_V 0x00000001U
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#define EFUSE_DSLP_LP_DBIAS_1_S 0
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/** EFUSE_LP_HP_DBIAS_VOL_GAP : R; bitpos: [5:1]; default: 0;
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* DBIAS gap between LP and HP
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*/
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#define EFUSE_LP_HP_DBIAS_VOL_GAP 0x0000001FU
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#define EFUSE_LP_HP_DBIAS_VOL_GAP_M (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S)
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#define EFUSE_LP_HP_DBIAS_VOL_GAP_V 0x0000001FU
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#define EFUSE_LP_HP_DBIAS_VOL_GAP_S 1
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/** EFUSE_RESERVED_1_134 : R; bitpos: [31:6]; default: 0;
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* reserved
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*/
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#define EFUSE_RESERVED_1_134 0x03FFFFFFU
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#define EFUSE_RESERVED_1_134_M (EFUSE_RESERVED_1_134_V << EFUSE_RESERVED_1_134_S)
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#define EFUSE_RESERVED_1_134_V 0x03FFFFFFU
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#define EFUSE_RESERVED_1_134_S 6
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/** EFUSE_RD_MAC_SYS5_REG register
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* Represents rd_mac_sys
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@@ -926,13 +981,34 @@ extern "C" {
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* Represents rd_sys_part1_data4
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*/
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#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
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/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
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* Temperature calibration data
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*/
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#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
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#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_4_S 0
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#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU
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#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
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#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU
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#define EFUSE_TEMPERATURE_SENSOR_S 0
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/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
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* ADC OCode
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*/
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#define EFUSE_OCODE 0x000000FFU
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#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
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#define EFUSE_OCODE_V 0x000000FFU
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#define EFUSE_OCODE_S 9
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/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
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* Average initcode of ADC1 atten0
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*/
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#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU
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#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
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#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU
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#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 17
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/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
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* Average initcode of ADC1 atten0
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*/
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#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x0000001FU
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#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
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#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x0000001FU
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#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 27
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/** EFUSE_RD_SYS_PART1_DATA5_REG register
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* Represents rd_sys_part1_data5
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@@ -614,15 +614,38 @@ typedef union {
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*/
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typedef union {
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struct {
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/** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
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* Reserved.
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* This field is only for internal debugging purposes. Do not use it in applications.
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/** trim_n_bias : R; bitpos: [4:0]; default: 0;
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* PADC CAL N bias
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*/
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uint32_t mac_reserved_2:18;
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/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
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* Represents the first 14-bit of zeroth part of system data.
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uint32_t trim_n_bias:5;
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/** trim_p_bias : R; bitpos: [9:5]; default: 0;
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* PADC CAL P bias
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*/
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uint32_t sys_data_part0_0:14;
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uint32_t trim_p_bias:5;
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/** active_hp_dbias : R; bitpos: [13:10]; default: 0;
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* Active HP DBIAS of fixed voltage
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*/
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uint32_t active_hp_dbias:4;
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/** active_lp_dbias : R; bitpos: [17:14]; default: 0;
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* Active LP DBIAS of fixed voltage
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*/
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uint32_t active_lp_dbias:4;
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/** lslp_hp_dbg : R; bitpos: [19:18]; default: 0;
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* LSLP HP DBG of fixed voltage
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*/
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uint32_t lslp_hp_dbg:2;
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/** lslp_hp_dbias : R; bitpos: [23:20]; default: 0;
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* LSLP HP DBIAS of fixed voltage
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*/
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uint32_t lslp_hp_dbias:4;
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/** dslp_lp_dbg : R; bitpos: [27:24]; default: 0;
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* DSLP LP DBG of fixed voltage
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*/
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uint32_t dslp_lp_dbg:4;
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/** dslp_lp_dbias : R; bitpos: [31:28]; default: 0;
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* DSLP LP DBIAS of fixed voltage
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*/
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uint32_t dslp_lp_dbias:4;
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};
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uint32_t val;
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} efuse_rd_mac_sys3_reg_t;
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@@ -632,10 +655,18 @@ typedef union {
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*/
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typedef union {
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struct {
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/** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
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* Represents the second 32-bit of zeroth part of system data.
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/** dslp_lp_dbias_1 : R; bitpos: [0]; default: 0;
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* DSLP LP DBIAS of fixed voltage
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*/
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uint32_t sys_data_part0_1:32;
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uint32_t dslp_lp_dbias_1:1;
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/** lp_hp_dbias_vol_gap : R; bitpos: [5:1]; default: 0;
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* DBIAS gap between LP and HP
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*/
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uint32_t lp_hp_dbias_vol_gap:5;
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/** reserved_1_134 : R; bitpos: [31:6]; default: 0;
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* reserved
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*/
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uint32_t reserved_1_134:26;
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};
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uint32_t val;
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} efuse_rd_mac_sys4_reg_t;
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@@ -655,19 +686,173 @@ typedef union {
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/** Group: block2 registers */
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/** Type of rd_sys_part1_datan register
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* Represents rd_sys_part1_datan
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/** Type of rd_sys_part1_data0 register
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* Represents rd_sys_part1_data0
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*/
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typedef union {
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struct {
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/** sys_data_part1_n : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** optional_unique_id : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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uint32_t sys_data_part1_n:32;
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uint32_t optional_unique_id:32;
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};
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uint32_t val;
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} efuse_rd_sys_part1_datan_reg_t;
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} efuse_rd_sys_part1_data0_reg_t;
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/** Type of rd_sys_part1_data1 register
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* Represents rd_sys_part1_data1
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*/
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typedef union {
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struct {
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/** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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uint32_t optional_unique_id_1:32;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data1_reg_t;
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/** Type of rd_sys_part1_data2 register
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* Represents rd_sys_part1_data2
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*/
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typedef union {
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struct {
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/** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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uint32_t optional_unique_id_2:32;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data2_reg_t;
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/** Type of rd_sys_part1_data3 register
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* Represents rd_sys_part1_data3
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*/
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typedef union {
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struct {
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/** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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uint32_t optional_unique_id_3:32;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data3_reg_t;
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/** Type of rd_sys_part1_data4 register
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* Represents rd_sys_part1_data4
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*/
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typedef union {
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struct {
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/** temperature_sensor : R; bitpos: [8:0]; default: 0;
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* Temperature calibration data
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*/
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uint32_t temperature_sensor:9;
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/** ocode : R; bitpos: [16:9]; default: 0;
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* ADC OCode
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*/
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uint32_t ocode:8;
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/** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0;
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* Average initcode of ADC1 atten0
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*/
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uint32_t adc1_ave_initcode_atten0:10;
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/** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0;
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* Average initcode of ADC1 atten0
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*/
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uint32_t adc1_ave_initcode_atten1:5;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data4_reg_t;
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/** Type of rd_sys_part1_data5 register
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* Represents rd_sys_part1_data5
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*/
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typedef union {
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struct {
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/** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0;
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* Average initcode of ADC1 atten0
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*/
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uint32_t adc1_ave_initcode_atten1_1:5;
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/** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0;
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* Average initcode of ADC1 atten0
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*/
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uint32_t adc1_ave_initcode_atten2:10;
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/** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0;
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* Average initcode of ADC1 atten0
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*/
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uint32_t adc1_ave_initcode_atten3:10;
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/** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
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* HI DOUT of ADC1 atten0
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*/
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uint32_t adc1_hi_dout_atten0:7;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data5_reg_t;
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/** Type of rd_sys_part1_data6 register
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* Represents rd_sys_part1_data6
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*/
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typedef union {
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struct {
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/** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
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* HI DOUT of ADC1 atten0
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*/
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uint32_t adc1_hi_dout_atten0_1:3;
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/** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
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* HI DOUT of ADC1 atten1
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*/
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uint32_t adc1_hi_dout_atten1:10;
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/** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
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* HI DOUT of ADC1 atten2
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*/
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uint32_t adc1_hi_dout_atten2:10;
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/** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
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* HI DOUT of ADC1 atten3
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*/
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uint32_t adc1_hi_dout_atten3:9;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data6_reg_t;
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/** Type of rd_sys_part1_data7 register
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* Represents rd_sys_part1_data7
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*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten3_1:1;
|
||||
/** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
|
||||
* Gap between ADC1 CH0 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch0_atten0_initcode_diff:4;
|
||||
/** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
|
||||
* Gap between ADC1 CH1 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch1_atten0_initcode_diff:4;
|
||||
/** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
|
||||
* Gap between ADC1 CH2 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch2_atten0_initcode_diff:4;
|
||||
/** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
|
||||
* Gap between ADC1 CH3 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch3_atten0_initcode_diff:4;
|
||||
/** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0;
|
||||
* Gap between ADC1 CH4 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch4_atten0_initcode_diff:4;
|
||||
/** adc1_ch5_atten0_initcode_diff : R; bitpos: [24:21]; default: 0;
|
||||
* Gap between ADC1 CH5 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch5_atten0_initcode_diff:4;
|
||||
/** reserved_2_249 : R; bitpos: [31:25]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_249:7;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data7_reg_t;
|
||||
|
||||
/** Group: block3 registers */
|
||||
/** Type of rd_usr_datan register
|
||||
@@ -3588,7 +3773,14 @@ typedef struct {
|
||||
volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
|
||||
volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
|
||||
volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
|
||||
volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8];
|
||||
volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
|
||||
volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
|
||||
volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
|
||||
volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
|
||||
volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
|
||||
volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
|
||||
volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
|
||||
volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
|
||||
volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8];
|
||||
volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8];
|
||||
volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8];
|
||||
|
||||
Reference in New Issue
Block a user