ESP32-H2: Last MR for g0 component support, (only hal left)

components/hal/CMakeLists.txt

@@ -191,6 +191,27 @@ if(NOT BOOTLOADER_BUILD)
                 "adc_hal_common.c"
                 )
     endif()
+
+    if(${target} STREQUAL "esp32h2")
+        list(APPEND srcs
+              "spi_flash_hal_gpspi.c"
+            )
+
+        # TODO: IDF-5310
+        list(REMOVE_ITEM srcs
+                "adc_oneshot_hal.c"
+                "adc_hal_common.c"
+                "spi_slave_hd_hal.c"
+                "spi_hal.c"
+                "spi_hal_iram.c"
+                "spi_slave_hal.c"
+                "spi_slave_hal_iram.c"
+                "esp32h2/brownout_hal.c"
+                "esp32h2/rtc_cntl_hal.c"
+                "timer_hal.c"
+                "timer_hal_iram.c"
+                )
+    endif()
 endif()
 
 idf_component_register(SRCS ${srcs}

components/hal/cache_hal.c

@@ -26,6 +26,8 @@
 #include "esp32h4/rom/cache.h"
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/cache.h"
 #endif
 
 /*------------------------------------------------------------------------------

components/hal/esp32h2/efuse_hal.c

@@ -3,3 +3,91 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
+#include "sdkconfig.h"
+#include <sys/param.h>
+#include "soc/soc_caps.h"
+#include "hal/assert.h"
+#include "hal/efuse_hal.h"
+#include "hal/efuse_ll.h"
+
+#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block))))
+#define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block))))
+
+uint32_t efuse_hal_get_major_chip_version(void)
+{
+    return efuse_ll_get_chip_wafer_version_major();
+}
+
+uint32_t efuse_hal_get_minor_chip_version(void)
+{
+    return efuse_ll_get_chip_wafer_version_minor();
+}
+
+/******************* eFuse control functions *************************/
+
+void efuse_hal_set_timing(uint32_t apb_freq_hz)
+{
+    (void) apb_freq_hz;
+    efuse_ll_set_pwr_off_num(0x190);
+}
+
+void efuse_hal_read(void)
+{
+    efuse_hal_set_timing(0);
+
+    efuse_ll_set_conf_read_op_code();
+    efuse_ll_set_read_cmd();
+
+    while (efuse_ll_get_read_cmd() != 0) { }
+    /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
+    while (efuse_ll_get_read_cmd() != 0) { }
+}
+
+void efuse_hal_clear_program_registers(void)
+{
+    ets_efuse_clear_program_registers();
+}
+
+void efuse_hal_program(uint32_t block)
+{
+    efuse_hal_set_timing(0);
+
+    efuse_ll_set_conf_write_op_code();
+    efuse_ll_set_pgm_cmd(block);
+
+    while (efuse_ll_get_pgm_cmd() != 0) { }
+
+    efuse_hal_clear_program_registers();
+    efuse_hal_read();
+}
+
+void efuse_hal_rs_calculate(const void *data, void *rs_values)
+{
+    ets_efuse_rs_calculate(data, rs_values);
+}
+
+/******************* eFuse control functions *************************/
+
+bool efuse_hal_is_coding_error_in_block(unsigned block)
+{
+    if (block == 0) {
+        for (unsigned i = 0; i < 5; i++) {
+            if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
+                return true;
+            }
+        }
+    } else if (block <= 10) {
+        // Fail bit (mask=0x8):
+        // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1, ------ (low)
+        // EFUSE_RD_RS_ERR1_REG:                                                      BLOCK9, BLOCK8
+        // Error num bits (mask=0x7):
+        // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
+        // EFUSE_RD_RS_ERR1_REG:                                                      BLOCK10, BLOCK9
+        // BLOCK10 is not presented in the error regs.
+        uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
+        uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4);
+        return (ESP_EFUSE_BLOCK_ERROR_BITS(err_fail_reg, block % 8) != 0) || (ESP_EFUSE_BLOCK_ERROR_NUM_BITS(err_num_reg, (block - 1) % 8) != 0);
+    }
+    return false;
+}

components/hal/esp32h2/include/hal/cache_ll.h

@@ -0,0 +1,197 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for Cache register operations
+
+#pragma once
+
+#include "soc/extmem_reg.h"
+#include "soc/ext_mem_defs.h"
+#include "hal/cache_types.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define CACHE_LL_DEFAULT_IBUS_MASK                  CACHE_BUS_IBUS0
+#define CACHE_LL_DEFAULT_DBUS_MASK                  CACHE_BUS_DBUS0
+
+#define CACHE_LL_L1_ACCESS_EVENT_MASK               (0x3f)
+#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC         (1<<5)
+#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT        (1<<4)
+#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC    (1<<3)
+#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT        (1<<2)
+#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC         (1<<1)
+#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC    (1<<0)
+
+#define CACHE_LL_L1_ILG_EVENT_MASK                  (0x23)
+#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT       (1<<5)
+#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT      (1<<1)
+#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT         (1<<0)
+
+
+/**
+ * @brief Get the buses of a particular cache that are mapped to a virtual address range
+ *
+ * External virtual address can only be accessed when the involved cache buses are enabled.
+ * This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
+ *
+ * @param cache_id          cache ID (when l1 cache is per core)
+ * @param vaddr_start       virtual address start
+ * @param len               vaddr length
+ */
+#if !BOOTLOADER_BUILD
+__attribute__((always_inline))
+#endif
+static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
+{
+    HAL_ASSERT(cache_id == 0);
+    cache_bus_mask_t mask = 0;
+
+    uint32_t vaddr_end = vaddr_start + len - 1;
+    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
+        mask |= CACHE_BUS_IBUS0;
+    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH(CONFIG_MMU_PAGE_SIZE)) {
+        mask |= CACHE_BUS_DBUS0;
+    } else {
+        HAL_ASSERT(0);          //Out of region
+    }
+
+    return mask;
+}
+
+/**
+ * Enable the Cache Buses
+ *
+ * @param cache_id    cache ID (when l1 cache is per core)
+ * @param mask        To know which buses should be enabled
+ */
+#if !BOOTLOADER_BUILD
+__attribute__((always_inline))
+#endif
+static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
+{
+    HAL_ASSERT(cache_id == 0);
+    //On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
+    HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
+
+    uint32_t ibus_mask = 0;
+    ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0;
+    REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask);
+
+    uint32_t dbus_mask = 0;
+    dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0;
+    REG_CLR_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask);
+}
+
+/**
+ * Disable the Cache Buses
+ *
+ * @param cache_id    cache ID (when l1 cache is per core)
+ * @param mask        To know which buses should be disabled
+ */
+__attribute__((always_inline))
+static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
+{
+    HAL_ASSERT(cache_id == 0);
+    //On esp32h2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
+    HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
+
+    uint32_t ibus_mask = 0;
+    ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_DCACHE_SHUT_DBUS0 : 0;
+    REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, ibus_mask);
+
+    uint32_t dbus_mask = 0;
+    dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_DBUS1 : 0;
+    REG_SET_BIT(EXTMEM_ICACHE_CTRL_REG, dbus_mask);
+}
+
+/*------------------------------------------------------------------------------
+ * Interrupt
+ *----------------------------------------------------------------------------*/
+/**
+ * @brief Enable Cache access error interrupt
+ *
+ * @param cache_id    Cache ID, not used on H2. For compabitlity
+ * @param mask        Interrupt mask
+ */
+static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
+{
+    // ESP32H2-TODO
+    // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask);
+}
+
+/**
+ * @brief Clear Cache access error interrupt status
+ *
+ * @param cache_id    Cache ID, not used on H2. For compabitlity
+ * @param mask        Interrupt mask
+ */
+static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
+{
+    // ESP32H2-TODO: IDF-6255
+    // SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask);
+}
+
+/**
+ * @brief Get Cache access error interrupt status
+ *
+ * @param cache_id    Cache ID, not used on H2. For compabitlity
+ * @param mask        Interrupt mask
+ *
+ * @return            Status mask
+ */
+static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
+{
+    // ESP32H2-TODO: IDF-6255
+    // return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask);
+    return 0;
+}
+
+/**
+ * @brief Enable Cache illegal error interrupt
+ *
+ * @param cache_id    Cache ID, not used on H2. For compabitlity
+ * @param mask        Interrupt mask
+ */
+static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask)
+{
+    // ESP32H2-TODO: IDF-6255
+    // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask);
+}
+
+/**
+ * @brief Clear Cache illegal error interrupt status
+ *
+ * @param cache_id    Cache ID, not used on H2. For compabitlity
+ * @param mask        Interrupt mask
+ */
+static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask)
+{
+    // ESP32H2-TODO: IDF-6255
+    // SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask);
+}
+
+/**
+ * @brief Get Cache illegal error interrupt status
+ *
+ * @param cache_id    Cache ID, not used on H2. For compabitlity
+ * @param mask        Interrupt mask
+ *
+ * @return            Status mask
+ */
+static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask)
+{
+    // ESP32H2-TODO: IDF-6255
+    // return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask);
+    return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/clk_gate_ll.h

@@ -0,0 +1,322 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/periph_defs.h"
+#include "soc/pcr_reg.h"
+#include "soc/dport_access.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
+{// ESP32H2-TODO: IDF-6400
+    switch (periph) {
+        case PERIPH_SARADC_MODULE:
+            return PCR_SARADC_CLK_EN;
+        case PERIPH_RMT_MODULE:
+            return PCR_RMT_CLK_EN;
+        case PERIPH_LEDC_MODULE:
+            return PCR_LEDC_CLK_EN;
+        case PERIPH_UART0_MODULE:
+            return PCR_UART0_CLK_EN;
+        case PERIPH_UART1_MODULE:
+            return PCR_UART1_CLK_EN;
+        case PERIPH_I2C0_MODULE:
+            return PCR_I2C0_CLK_EN;
+        case PERIPH_I2C1_MODULE:
+            return PCR_I2C1_CLK_EN;
+        case PERIPH_I2S1_MODULE:
+            return PCR_I2S_CLK_EN;
+        case PERIPH_TIMG0_MODULE:
+            return PCR_TG0_CLK_EN;
+        case PERIPH_TIMG1_MODULE:
+            return PCR_TG1_CLK_EN;
+        case PERIPH_UHCI0_MODULE:
+            return PCR_UHCI_CLK_EN;
+        case PERIPH_SYSTIMER_MODULE:
+            return PCR_SYSTIMER_CLK_EN;
+        case PERIPH_SPI_MODULE:
+            return PCR_MSPI_CLK_EN;
+        case PERIPH_SPI2_MODULE:
+            return PCR_SPI2_CLK_EN;
+        case PERIPH_TWAI0_MODULE:
+            return PCR_TWAI0_CLK_EN;
+        case PERIPH_GDMA_MODULE:
+            return PCR_GDMA_CLK_EN;
+        case PERIPH_AES_MODULE:
+            return PCR_AES_CLK_EN;
+        case PERIPH_SHA_MODULE:
+            return PCR_SHA_CLK_EN;
+        case PERIPH_RSA_MODULE:
+            return PCR_RSA_CLK_EN;
+        case PERIPH_HMAC_MODULE:
+            return PCR_HMAC_CLK_EN;
+        case PERIPH_DS_MODULE:
+            return PCR_DS_CLK_EN;
+        // case PERIPH_RNG_MODULE:
+        //     return PCR_WIFI_CLK_RNG_EN;
+        // case PERIPH_WIFI_MODULE:
+        //     return PCR_WIFI_CLK_WIFI_EN_M;
+        // case PERIPH_BT_MODULE:
+        //     return PCR_WIFI_CLK_BT_EN_M;
+        // case PERIPH_WIFI_BT_COMMON_MODULE:
+        //     return PCR_WIFI_CLK_WIFI_BT_COMMON_M;
+        // case PERIPH_BT_BASEBAND_MODULE:
+        //     return PCR_BT_BASEBAND_EN;
+        // case PERIPH_BT_LC_MODULE:
+        //     return PCR_BT_LC_EN;
+        default:
+            return 0;
+    }
+}
+
+static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool enable)
+{
+// ESP32H2-TODO: IDF-6400
+    (void)enable; // unused
+
+    switch (periph) {
+        case PERIPH_SARADC_MODULE:
+            return PCR_SARADC_RST_EN;
+        case PERIPH_RMT_MODULE:
+            return PCR_RMT_RST_EN;
+        case PERIPH_LEDC_MODULE:
+            return PCR_LEDC_RST_EN;
+        case PERIPH_UART0_MODULE:
+            return PCR_UART0_RST_EN;
+        case PERIPH_UART1_MODULE:
+            return PCR_UART1_RST_EN;
+        case PERIPH_I2C0_MODULE:
+            return PCR_I2C0_RST_EN;
+        case PERIPH_I2C1_MODULE:
+            return PCR_I2C1_RST_EN;
+        case PERIPH_I2S1_MODULE:
+            return PCR_I2S_RST_EN;
+        case PERIPH_TIMG0_MODULE:
+            return PCR_TG0_RST_EN;
+        case PERIPH_TIMG1_MODULE:
+            return PCR_TG1_RST_EN;
+        case PERIPH_UHCI0_MODULE:
+            return PCR_UHCI_RST_EN;
+        case PERIPH_SYSTIMER_MODULE:
+            return PCR_SYSTIMER_RST_EN;
+        case PERIPH_SPI_MODULE:
+            return PCR_MSPI_RST_EN;
+        case PERIPH_SPI2_MODULE:
+            return PCR_SPI2_RST_EN;
+        case PERIPH_TWAI0_MODULE:
+            return PCR_TWAI0_RST_EN;
+        case PERIPH_GDMA_MODULE:
+            return PCR_GDMA_RST_EN;
+        case PERIPH_AES_MODULE:
+        if (enable == true) {
+            // Clear reset on digital signature, otherwise AES unit is held in reset also.
+                return (PCR_AES_RST_EN | PCR_DS_RST_EN);
+        } else {
+                //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
+                return PCR_AES_RST_EN;
+        }
+        case PERIPH_SHA_MODULE:
+        if (enable == true) {
+            // Clear reset on digital signature and HMAC, otherwise SHA is held in reset
+                return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN);
+        } else {
+            // Don't assert reset on secure boot, otherwise AES is held in reset
+                return PCR_SHA_RST_EN;
+        }
+        case PERIPH_RSA_MODULE:
+        if (enable == true) {
+            /* also clear reset on digital signature, otherwise RSA is held in reset */
+                return (PCR_RSA_RST_EN | PCR_DS_RST_EN);
+        } else {
+            /* don't reset digital signature unit, as this resets AES also */
+                return PCR_RSA_RST_EN;
+        }
+        case PERIPH_HMAC_MODULE:
+            return PCR_HMAC_RST_EN;
+        case PERIPH_DS_MODULE:
+            return PCR_DS_RST_EN;
+        // case PERIPH_RNG_MODULE:
+        //     return PCR_WIFI_CLK_RNG_EN;
+        // case PERIPH_WIFI_MODULE:
+        //     return PCR_WIFI_CLK_WIFI_EN_M;
+        // case PERIPH_BT_MODULE:
+        //     return PCR_WIFI_CLK_BT_EN_M;
+        // case PERIPH_WIFI_BT_COMMON_MODULE:
+        //     return PCR_WIFI_CLK_WIFI_BT_COMMON_M;
+        // case PERIPH_BT_BASEBAND_MODULE:
+        //     return PCR_BT_BASEBAND_EN;
+        // case PERIPH_BT_LC_MODULE:
+        //     return PCR_BT_LC_EN;
+        default:
+            return 0;
+    }
+}
+
+static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
+{// ESP32H2-TODO: IDF-6400
+    switch (periph) {
+    // case PERIPH_RNG_MODULE:
+    // case PERIPH_WIFI_MODULE:
+    // case PERIPH_BT_MODULE:
+    // case PERIPH_WIFI_BT_COMMON_MODULE:
+    // case PERIPH_BT_BASEBAND_MODULE:
+    // case PERIPH_BT_LC_MODULE:
+    //      return SYSTEM_WIFI_CLK_EN_REG;
+
+        case PERIPH_SARADC_MODULE:
+            return PCR_SARADC_CONF_REG;
+        case PERIPH_RMT_MODULE:
+            return PCR_RMT_CONF_REG;
+        case PERIPH_LEDC_MODULE:
+            return PCR_LEDC_CONF_REG;
+        case PERIPH_UART0_MODULE:
+            return PCR_UART0_CONF_REG;
+        case PERIPH_UART1_MODULE:
+            return PCR_UART1_CONF_REG;
+        case PERIPH_I2C0_MODULE:
+            return PCR_I2C0_CONF_REG;
+        case PERIPH_I2C1_MODULE:
+            return PCR_I2C1_CONF_REG;
+        case PERIPH_I2S1_MODULE:
+            return PCR_I2S_CONF_REG;
+        case PERIPH_TIMG0_MODULE:
+            return PCR_TIMERGROUP0_CONF_REG;
+        case PERIPH_TIMG1_MODULE:
+            return PCR_TIMERGROUP1_CONF_REG;
+        case PERIPH_UHCI0_MODULE:
+            return PCR_UHCI_CONF_REG;
+        case PERIPH_SYSTIMER_MODULE:
+            return PCR_SYSTIMER_CONF_REG;
+        case PERIPH_SPI_MODULE:
+            return PCR_MSPI_CONF_REG;
+        case PERIPH_SPI2_MODULE:
+            return PCR_SPI2_CONF_REG;
+        case PERIPH_TWAI0_MODULE:
+            return PCR_TWAI0_CONF_REG;
+        case PERIPH_GDMA_MODULE:
+            return PCR_GDMA_CONF_REG;
+        case PERIPH_AES_MODULE:
+            return PCR_AES_CONF_REG;
+        case PERIPH_SHA_MODULE:
+            return PCR_SHA_CONF_REG;
+        case PERIPH_RSA_MODULE:
+            return PCR_RSA_CONF_REG;
+        case PERIPH_HMAC_MODULE:
+            return PCR_HMAC_CONF_REG;
+        case PERIPH_DS_MODULE:
+            return PCR_DS_CONF_REG;
+    default:
+        return 0;
+    }
+}
+
+static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
+{
+    // ESP32H2-TODO: IDF-6400
+    switch (periph) {
+        case PERIPH_SARADC_MODULE:
+            return PCR_SARADC_CONF_REG;
+        case PERIPH_RMT_MODULE:
+            return PCR_RMT_CONF_REG;
+        case PERIPH_LEDC_MODULE:
+            return PCR_LEDC_CONF_REG;
+        case PERIPH_UART0_MODULE:
+            return PCR_UART0_CONF_REG;
+        case PERIPH_UART1_MODULE:
+            return PCR_UART1_CONF_REG;
+        case PERIPH_I2C0_MODULE:
+            return PCR_I2C0_CONF_REG;
+        case PERIPH_I2C1_MODULE:
+            return PCR_I2C1_CONF_REG;
+        case PERIPH_I2S1_MODULE:
+            return PCR_I2S_CONF_REG;
+        case PERIPH_TIMG0_MODULE:
+            return PCR_TIMERGROUP0_CONF_REG;
+        case PERIPH_TIMG1_MODULE:
+            return PCR_TIMERGROUP1_CONF_REG;
+        case PERIPH_UHCI0_MODULE:
+            return PCR_UHCI_CONF_REG;
+        case PERIPH_SYSTIMER_MODULE:
+            return PCR_SYSTIMER_CONF_REG;
+        case PERIPH_SPI_MODULE:
+            return PCR_MSPI_CONF_REG;
+        case PERIPH_SPI2_MODULE:
+            return PCR_SPI2_CONF_REG;
+        case PERIPH_TWAI0_MODULE:
+            return PCR_TWAI0_CONF_REG;
+        case PERIPH_GDMA_MODULE:
+            return PCR_GDMA_CONF_REG;
+        case PERIPH_AES_MODULE:
+            return PCR_AES_CONF_REG;
+        case PERIPH_SHA_MODULE:
+            return PCR_SHA_CONF_REG;
+        case PERIPH_RSA_MODULE:
+            return PCR_RSA_CONF_REG;
+        case PERIPH_HMAC_MODULE:
+            return PCR_HMAC_CONF_REG;
+        case PERIPH_DS_MODULE:
+            return PCR_DS_CONF_REG;
+    default:
+        return 0;
+    }
+}
+
+static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
+{
+    DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
+    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
+}
+
+static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
+{
+    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
+    DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+}
+
+static inline void periph_ll_wifi_bt_module_enable_clk_clear_rst(void)
+{
+    // DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// ESP32H2-TODO: IDF-6400
+    // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
+
+static inline void periph_ll_wifi_bt_module_disable_clk_set_rst(void)
+{
+    // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);// ESP32H2-TODO: IDF-6400
+    // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
+
+static inline void periph_ll_reset(periph_module_t periph)
+{
+    DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+}
+
+static inline bool periph_ll_periph_enabled(periph_module_t periph)
+{
+    return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
+           DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
+}
+
+static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
+{
+    // DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);// ESP32H2-TODO: IDF-6400
+    // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
+
+static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
+{
+    // DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);// ESP32H2-TODO: IDF-6400
+    // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
+}
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/clk_tree_ll.h

@@ -0,0 +1,568 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/rtc.h"
+#include "soc/pcr_reg.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_bbpll.h"
+#include "hal/assert.h"
+#include "hal/log.h"
+#include "esp32h2/rom/rtc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MHZ                 (1000000)
+
+#define CLK_LL_PLL_80M_FREQ_MHZ    (80)
+#define CLK_LL_PLL_160M_FREQ_MHZ   (160)
+
+#define CLK_LL_PLL_320M_FREQ_MHZ   (320)
+#define CLK_LL_PLL_480M_FREQ_MHZ   (480)
+
+#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
+    .dac = 3, \
+    .dres = 3, \
+    .dgm = 3, \
+    .dbuf = 1, \
+}
+
+/**
+ * @brief XTAL32K_CLK enable modes
+ */
+typedef enum {
+    CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL,       //!< Enable the external 32kHz crystal for XTAL32K_CLK
+    CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL,      //!< Enable the external clock signal for XTAL32K_CLK
+    CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP,     //!< Bootstrap the crystal oscillator for faster XTAL32K_CLK start up */
+} clk_ll_xtal32k_enable_mode_t;
+
+/**
+ * @brief XTAL32K_CLK configuration structure
+ */
+typedef struct {
+    uint32_t dac : 6;
+    uint32_t dres : 3;
+    uint32_t dgm : 3;
+    uint32_t dbuf: 1;
+} clk_ll_xtal32k_config_t;
+
+/**
+ * @brief Power up BBPLL circuit
+ */
+static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Power down BBPLL circuit
+ */
+static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Enable the 32kHz crystal oscillator
+ *
+ * @param mode Used to determine the xtal32k configuration parameters
+ */
+static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Disable the 32kHz crystal oscillator
+ */
+static inline void clk_ll_xtal32k_disable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Get the state of the 32kHz crystal clock
+ *
+ * @return True if the 32kHz XTAL is enabled
+ */
+static inline bool clk_ll_xtal32k_is_enabled(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Enable the internal oscillator output for RC_FAST_CLK
+ */
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Disable the internal oscillator output for RC_FAST_CLK
+ */
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Get the state of the internal oscillator for RC_FAST_CLK
+ *
+ * @return True if the oscillator is enabled
+ */
+static inline bool clk_ll_rc_fast_is_enabled(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 1;
+}
+
+/**
+ * @brief Enable the output from the internal oscillator to be passed into a configurable divider,
+ * which by default divides the input clock frequency by 256. i.e. RC_FAST_D256_CLK = RC_FAST_CLK / 256
+ *
+ * Divider values other than 256 may be configured, but this facility is not currently needed,
+ * so is not exposed in the code.
+ * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.
+ */
+static inline void clk_ll_rc_fast_d256_enable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Disable the output from the internal oscillator to be passed into a configurable divider.
+ * i.e. RC_FAST_D256_CLK = RC_FAST_CLK / 256
+ *
+ * Disabling this divider could reduce power consumption.
+ */
+static inline void clk_ll_rc_fast_d256_disable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Get the state of the divider which is applied to the output from the internal oscillator (RC_FAST_CLK)
+ *
+ * @return True if the divided output is enabled
+ */
+static inline bool clk_ll_rc_fast_d256_is_enabled(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 1;
+}
+
+/**
+ * @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_rc_fast_digi_enable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_rc_fast_digi_disable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Get the state of the digital RC_FAST_CLK
+ *
+ * @return True if the digital RC_FAST_CLK is enabled
+ */
+static inline bool clk_ll_rc_fast_digi_is_enabled(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_rc_fast_d256_digi_enable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_rc_fast_d256_digi_disable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_xtal32k_digi_enable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_xtal32k_digi_disable(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Get the state of the digital XTAL32K_CLK
+ *
+ * @return True if the digital XTAL32K_CLK is enabled
+ */
+static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Get PLL_CLK frequency
+ *
+ * @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid.
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Set BBPLL frequency from XTAL source (Digital part)
+ *
+ * @param pll_freq_mhz PLL frequency, in MHz
+ */
+static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Set BBPLL frequency from XTAL source (Analog part)
+ *
+ * @param pll_freq_mhz PLL frequency, in MHz
+ * @param xtal_freq_mhz XTAL frequency, in MHz
+ */
+static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Select the clock source for CPU_CLK
+ *
+ * @param in_sel One of the clock sources in soc_cpu_clk_src_t
+ */
+static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel)
+{
+    // ESP32H2-TODO: IDF-6401
+    switch (in_sel) {
+    case SOC_CPU_CLK_SRC_XTAL:
+        REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 0);
+        break;
+    case SOC_CPU_CLK_SRC_PLL:
+        REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 1);
+        break;
+    case SOC_CPU_CLK_SRC_RC_FAST://FOSC
+        REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 2);
+        break;
+    default:
+        // Unsupported CPU_CLK mux input sel
+        abort();
+    }
+}
+
+/**
+ * @brief Get the clock source for CPU_CLK
+ *
+ * @return Currently selected clock source (one of soc_cpu_clk_src_t values)
+ */
+static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    uint32_t clk_sel = REG_GET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL);
+    switch (clk_sel) {
+    case 0:
+        return SOC_CPU_CLK_SRC_XTAL;
+    case 1:
+        return SOC_CPU_CLK_SRC_PLL;
+    case 2://FOSC
+        return SOC_CPU_CLK_SRC_RC_FAST;
+    default:
+        // Invalid SOC_CLK_SEL value
+        return SOC_CPU_CLK_SRC_INVALID;
+    }
+}
+
+#include "hal/uart_types.h"
+static inline __attribute__((always_inline)) void clk_ll_uart_set_sclk(uint32_t uart_num, uart_sclk_t source_clk)
+{
+    // switch (source_clk) {
+    //     default:
+    //     case UART_SCLK_APB:
+    //         REG_SET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL, 1);
+    //         break;
+    //     case UART_SCLK_RTC:
+    //         REG_SET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL, 2);
+    //         break;
+    //     case UART_SCLK_XTAL:
+    //         REG_SET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL, 3);
+    //         break;
+    // }
+}
+
+static inline __attribute__((always_inline)) void clk_ll_uart_get_sclk(uint32_t uart_num, uart_sclk_t *source_clk)
+{
+    // switch (REG_GET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL)) {
+    //     default:
+    //     case 1:
+    //         *source_clk = UART_SCLK_APB;
+    //         break;
+    //     case 2:
+    //         *source_clk = UART_SCLK_RTC;
+    //         break;
+    //     case 3:
+    //         *source_clk = UART_SCLK_XTAL;
+    //         break;
+    // }
+}
+
+static inline uint32_t clk_ll_get_uart_sclk_freq(uint32_t uart_num)
+{
+    // switch (REG_GET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL)) {
+    //     default:
+    //     case 1:
+    //         return APB_CLK_FREQ;
+    //     case 2:
+    //         return RTC_CLK_FREQ;
+    //     case 3:
+    //         return XTAL_CLK_FREQ;
+    // }
+    return 0;
+}
+
+static inline __attribute__((always_inline)) void clk_ll_uart_set_sclk_div_num(uint8_t uart_num, uint32_t val)
+{
+    // REG_SET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_DIV_NUM, val);
+}
+
+static inline __attribute__((always_inline)) uint32_t clk_ll_uart_get_sclk_div_num(uint8_t uart_num)
+{
+    return 0;//REG_GET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_DIV_NUM);
+}
+
+/**
+ * @brief Set CPU frequency from PLL clock
+ *
+ * @param cpu_mhz CPU frequency value, in MHz
+ */
+static inline __attribute__((always_inline)) void clk_ll_cpu_set_freq_mhz_from_pll(uint32_t cpu_mhz)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Get CPU_CLK frequency from PLL_CLK source
+ *
+ * @return CPU clock frequency, in MHz. Returns 0 if register field value is invalid.
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_freq_mhz_from_pll(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Set CPU_CLK's XTAL/FAST_RC clock source path divider
+ *
+ * @param divider Divider. Usually this divider is set to 1 in bootloader stage. PRE_DIV_CNT = divider - 1.
+ */
+static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider)
+{
+    // ESP32H2-TODO: IDF-6401: not configurable for 761, fixed at 3 for HS, 1 for LS
+}
+
+/**
+ * @brief Get CPU_CLK's XTAL/FAST_RC clock source path divider
+ *
+ * @return Divider. Divider = (PRE_DIV_CNT + 1).
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Select the clock source for RTC_SLOW_CLK
+ *
+ * @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
+ */
+static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Get the clock source for RTC_SLOW_CLK
+ *
+ * @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
+ */
+static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Select the clock source for RTC_FAST_CLK
+ *
+ * @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
+ */
+static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Get the clock source for RTC_FAST_CLK
+ *
+ * @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
+ */
+static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Set RC_FAST_CLK divider. The output from the divider is passed into rtc_fast_clk MUX.
+ *
+ * @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
+ */
+static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Get RC_FAST_CLK divider
+ *
+ * @return Divider. Divider = (CK8M_DIV_SEL + 1).
+ */
+static inline uint32_t clk_ll_rc_fast_get_divider(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Set RC_SLOW_CLK divider
+ *
+ * @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
+ */
+static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/************************* RTC STORAGE REGISTER STORE/LOAD **************************/
+/**
+ * @brief Store XTAL_CLK frequency in RTC storage register
+ *
+ * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
+ * halves. These are the routines to work with that representation.
+ *
+ * @param xtal_freq_mhz XTAL frequency, in MHz
+ */
+static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Load XTAL_CLK frequency from RTC storage register
+ *
+ * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
+ * halves. These are the routines to work with that representation.
+ *
+ * @return XTAL frequency, in MHz. Returns 0 if value in reg is invalid.
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Store APB_CLK frequency in RTC storage register
+ *
+ * Value of RTC_APB_FREQ_REG is stored as two copies in lower and upper 16-bit
+ * halves. These are the routines to work with that representation.
+ *
+ * @param apb_freq_hz APB frequency, in Hz
+ */
+static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint32_t apb_freq_hz)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Load APB_CLK frequency from RTC storage register
+ *
+ * Value of RTC_APB_FREQ_REG is stored as two copies in lower and upper 16-bit
+ * halves. These are the routines to work with that representation.
+ *
+ * @return The stored APB frequency, in Hz
+ */
+static inline uint32_t clk_ll_apb_load_freq_hz(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+/**
+ * @brief Store RTC_SLOW_CLK calibration value in RTC storage register
+ *
+ * Value of RTC_SLOW_CLK_CAL_REG has to be in the same format as returned by rtc_clk_cal (microseconds,
+ * in Q13.19 fixed-point format).
+ *
+ * @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
+ */
+static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+/**
+ * @brief Load the calibration value of RTC_SLOW_CLK frequency from RTC storage register
+ *
+ * This value gets updated (i.e. rtc slow clock gets calibrated) every time RTC_SLOW_CLK source switches
+ *
+ * @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
+ */
+static inline uint32_t clk_ll_rtc_slow_load_cal(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/efuse_hal.h

@@ -0,0 +1,69 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "hal/efuse_ll.h"
+#include_next "hal/efuse_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief get chip version
+ */
+uint32_t efuse_hal_get_chip_revision(void);
+
+/**
+ * @brief set eFuse timings
+ *
+ * @param apb_freq_hz APB frequency in Hz
+ */
+void efuse_hal_set_timing(uint32_t apb_freq_hz);
+
+/**
+ * @brief trigger eFuse read operation
+ */
+void efuse_hal_read(void);
+
+/**
+ * @brief clear registers for programming eFuses
+ */
+void efuse_hal_clear_program_registers(void);
+
+/**
+ * @brief burn eFuses written in programming registers (one block at once)
+ *
+ * @param block block number
+ */
+void efuse_hal_program(uint32_t block);
+
+/**
+ * @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
+ *
+ * @param data Pointer to data buffer (length 32 bytes)
+ * @param rs_values Pointer to write encoded data to (length 12 bytes)
+ */
+void efuse_hal_rs_calculate(const void *data, void *rs_values);
+
+/**
+ * @brief Checks coding error in a block
+ *
+ * @param block Index of efuse block
+ *
+ * @return True  - block has an error.
+ *         False - no error.
+ */
+bool efuse_hal_is_coding_error_in_block(unsigned block);
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/efuse_ll.h

@@ -0,0 +1,129 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/efuse_periph.h"
+#include "hal/assert.h"
+#include "esp32h2/rom/efuse.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Always inline these functions even no gcc optimization is applied.
+
+//// ESP32H2-TODO: efuse support IDF-6252
+
+/******************* eFuse fields *************************/
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
+{
+    return 0;//EFUSE.rd_repeat_data1.spi_boot_crypt_cnt;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
+{
+    return 0;//EFUSE.rd_repeat_data1.wdt_delay_sel;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
+{
+    return 0;//EFUSE.rd_mac_sys_0;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
+{
+    return 0;//EFUSE.rd_mac_sys_1.mac_1;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
+{
+    return 0;//EFUSE.rd_repeat_data2.secure_boot_en;
+}
+
+// use efuse_hal_get_major_chip_version() to get major chip version
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
+{
+    return 0;//EFUSE.rd_mac_sys_5.wafer_version_major;
+}
+
+// use efuse_hal_get_minor_chip_version() to get minor chip version
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
+{
+    return 0;//(EFUSE.rd_mac_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_sys_3.wafer_version_minor_low;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
+{
+    return 0;//EFUSE.rd_repeat_data4.disable_wafer_version_major;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
+{
+    return 0;//EFUSE.rd_sys_part1_data4.blk_version_major;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
+{
+    return 0;//EFUSE.rd_mac_sys_3.blk_version_minor;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
+{
+    return 0;//EFUSE.rd_repeat_data4.disable_blk_version_major;
+}
+
+__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
+{
+    return 0;//EFUSE.rd_mac_sys_3.pkg_version;
+}
+
+/******************* eFuse control functions *************************/
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
+{
+    return 0;//EFUSE.cmd.read_cmd;
+}
+
+__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
+{
+    return 0;//EFUSE.cmd.pgm_cmd;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
+{
+    // EFUSE.cmd.read_cmd = 1;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
+{
+    // HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
+    // EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
+{
+    // EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
+{
+    // EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
+}
+
+__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
+{
+    // EFUSE.wr_tim_conf2.pwr_off_num = value;
+}
+
+/******************* eFuse control functions *************************/
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/gpio_ll.h

@@ -0,0 +1,615 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use in application code.
+ * See readme.md in soc/include/hal/readme.md
+ ******************************************************************************/
+
+// The LL layer for ESP32-H2 GPIO register operations
+
+#pragma once
+
+#include "soc/soc.h"
+#include "soc/gpio_periph.h"
+#include "soc/gpio_struct.h"
+#include "soc/lp_aon_reg.h"
+#include "soc/pmu_reg.h"
+#include "hal/gpio_types.h"
+#include <stdlib.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// ESP32H2-TODO: comment some code, please add support on gpio, IDF-6227
+
+/*
+ * The following defines are used to disable USB JTAG when pins 18 and pins 19
+ * are set to be used as GPIO.
+ * See gpio_pad_select_gpio() below.
+ *
+ * TODO: Delete these definitions once the USB device registers definition is
+ * merged.
+ */
+#define USB_DEVICE_CONF0_REG        (0x60043018)
+#define USB_DEVICE_USB_PAD_ENABLE   (BIT(14))
+
+// Get GPIO hardware instance with giving gpio num
+#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
+
+#define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
+#define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+/**
+  * @brief Enable pull-up on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+}
+
+/**
+  * @brief Disable pull-up on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+}
+
+/**
+  * @brief Enable pull-down on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+}
+
+/**
+  * @brief Disable pull-down on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+}
+
+/**
+ * @brief  GPIO set interrupt trigger type
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  intr_type Interrupt type, select from gpio_int_type_t
+ */
+static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+{
+    // hw->pin[gpio_num].int_type = intr_type;
+    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
+}
+
+/**
+  * @brief Get GPIO interrupt status
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param core_id interrupt core id
+  * @param status interrupt status
+  */
+static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
+{
+    *status = hw->pcpu_int.val;
+}
+
+/**
+  * @brief Get GPIO interrupt status high
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param core_id interrupt core id
+  * @param status interrupt status high
+  */
+static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
+{
+    *status = 0; // Less than 32 GPIOs in ESP32-H2
+}
+
+/**
+  * @brief Clear GPIO interrupt status
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param mask interrupt status clear mask
+  */
+static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
+{
+    // hw->status_w1tc = mask;
+}
+
+/**
+  * @brief Clear GPIO interrupt status high
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param mask interrupt status high clear mask
+  */
+static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
+{
+    // Not supported on H2
+}
+
+/**
+ * @brief  Enable GPIO module interrupt signal
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  core_id Interrupt enabled CPU to corresponding ID
+ * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ */
+static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
+{
+// ESP32H2-TODO: IDF-6227 updated struct file not support yet
+#if 0
+    if (core_id == 0) {
+        GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+    } else {
+        // GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA;     //enable pro cpu intr
+    }
+#endif
+}
+
+/**
+ * @brief  Disable GPIO module interrupt signal
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ */
+static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
+    // hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
+}
+
+/**
+  * @brief Disable input mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable input mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable output mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // hw->enable_w1tc = (0x1 << gpio_num);
+    // // Ensure no other output signal is routed via GPIO matrix to this pin
+    // REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
+    //           SIG_GPIO_OUT_IDX);
+}
+
+/**
+  * @brief Enable output mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // hw->enable_w1ts = (0x1 << gpio_num);
+}
+
+/**
+  * @brief Disable open-drain mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
+    // hw->pin[gpio_num].pad_driver = 0;
+}
+
+/**
+  * @brief Enable open-drain mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
+    // hw->pin[gpio_num].pad_driver = 1;
+}
+
+/**
+ * @brief  GPIO set output level
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  level Output level. 0: low ; 1: high
+ */
+static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level)
+{
+    // if (level) {
+    //     hw->out_w1ts = (1 << gpio_num);
+    // } else {
+    //     hw->out_w1tc = (1 << gpio_num);
+    // }
+}
+
+/**
+ * @brief  GPIO get input level
+ *
+ * @warning If the pad is not configured for input (or input and output) the returned value is always 0.
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ *
+ * @return
+ *     - 0 the GPIO input level is 0
+ *     - 1 the GPIO input level is 1
+ */
+static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    return 0;//(hw->in >> gpio_num) & 0x1;
+}
+
+/**
+ * @brief Enable GPIO wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number.
+ * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
+ */
+static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+// ESP32H2-TODO: IDF-6227 updated struct file not support yet
+#if 0
+    hw->pin[gpio_num].int_type = intr_type;
+    hw->pin[gpio_num].wakeup_enable = 0x1;
+#endif
+}
+
+/**
+ * @brief Disable GPIO wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
+    // hw->pin[gpio_num].wakeup_enable = 0;
+}
+
+/**
+  * @brief Set GPIO pad drive capability
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Drive capability of the pad
+  */
+static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength)
+{
+    SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
+}
+
+/**
+  * @brief Get GPIO pad drive capability
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Pointer to accept drive capability of the pad
+  */
+static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
+{
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+}
+
+/**
+  * @brief Enable all digital gpio pad hold function during Deep-sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  */
+static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
+{
+    // ESP32H2 has removed deepsleep and replace with software backup sleep
+}
+
+/**
+  * @brief Disable all digital gpio pad hold function during Deep-sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  */
+static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
+{
+    // ESP32H2 has removed deepsleep and replace with software backup sleep
+}
+
+/**
+  * @brief Enable gpio pad hold function.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  */
+static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    if (gpio_num <32){
+        SET_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]);
+    } else if (gpio_num <= MAX_PAD_GPIO_NUM){
+        SET_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]);
+    }
+}
+
+/**
+  * @brief Disable gpio pad hold function.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  */
+static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    if (gpio_num <32){
+        CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]);
+    } else if (gpio_num <= MAX_PAD_GPIO_NUM){
+        CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]);
+    }
+}
+
+/**
+  * @brief Set pad input to a peripheral signal through the IOMUX.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number of the pad.
+  * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
+  */
+static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
+{
+    hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
+    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]);
+}
+
+/**
+ * @brief  Select a function for the pin in the IOMUX
+ *
+ * @param  pin_name Pin name to configure
+ * @param  func Function to assign to the pin
+ */
+static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
+{
+    if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
+        CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE);
+    }
+    PIN_FUNC_SELECT(pin_name, func);
+}
+
+/**
+  * @brief Set peripheral output to an GPIO pad through the IOMUX.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num gpio_num GPIO number of the pad.
+  * @param func The function number of the peripheral pin to output pin.
+  *        One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``.
+  * @param oen_inv True if the output enable needs to be inverted, otherwise False.
+  */
+static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
+{
+#if 0
+    hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
+    hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
+    gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
+#endif
+}
+
+static inline void gpio_ll_force_hold_all(void)
+{
+    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_HP_PAD_HOLD_ALL);
+    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_LP_PAD_HOLD_ALL);
+}
+
+static inline void gpio_ll_force_unhold_all(void)
+{
+    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_HP_PAD_HOLD_ALL);
+    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_LP_PAD_HOLD_ALL);
+}
+
+/**
+  * @brief Enable GPIO pin used for wakeup from sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO pin used for wakeup from sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO pull-up in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO pull-up in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO pull-down in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO pull-down in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO input in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO input in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO output in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO output in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    // ESP32H2-TODO: IDF-6227
+    // PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+ * @brief Enable GPIO deep-sleep wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number.
+ * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
+ */
+static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+{
+    if (gpio_num > GPIO_NUM_5) {
+        abort(); // gpio lager than 5 doesn't support.
+    }
+    // SET_PERI_REG_MASK( LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE);
+    // REG_SET_FIELD( LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE, intr_type);
+}
+
+/**
+ * @brief Disable GPIO deep-sleep wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    if (gpio_num > GPIO_NUM_5) {
+        abort(); // gpio lager than 5 doesn't support.
+    }
+    // ESP32H2 LP_IO check: IDF-6403
+    // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE);
+    // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE);
+}
+
+/**
+ * @brief Get the status of whether an IO is used for deep-sleep wake-up.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ * @return True if the pin is enabled to wake up from deep-sleep
+ */
+static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // ESP32H2 LP_IO check: IDF-6403
+    // HAL_ASSERT(gpio_num <= GPIO_NUM_7 && "gpio larger than 7 does not support deep sleep wake-up function");
+    // On ESP32-H2, (lp_io pin number) == (gpio pin number)
+    return true;//LP_IO.pin[gpio_num].wakeup_enable;
+}
+
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/gpspi_flash_ll.h

@@ -0,0 +1,409 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in soc/include/hal/readme.md
+ ******************************************************************************/
+
+// The Lowlevel layer for SPI Flash
+
+#pragma once
+
+#include <stdlib.h>
+#include "soc/spi_periph.h"
+#include "soc/spi_struct.h"
+#include "hal/spi_types.h"
+#include "hal/spi_flash_types.h"
+#include <sys/param.h> // For MIN/MAX
+#include <stdbool.h>
+#include <string.h>
+#include "hal/misc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//NOTE: These macros are changed on h2 for build. MODIFY these when bringup flash.
+#define gpspi_flash_ll_get_hw(host_id)  ( ((host_id)==SPI2_HOST) ? &GPSPI2 : ({abort();(spi_dev_t*)0;}) )
+#define gpspi_flash_ll_hw_get_id(dev)   ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 )
+
+typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t;
+#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ  (80)
+
+/*------------------------------------------------------------------------------
+ * Control
+ *----------------------------------------------------------------------------*/
+/**
+ * Reset peripheral registers before configuration and starting control
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
+{
+    dev->user.val = 0;
+    dev->ctrl.val = 0;
+
+    dev->clk_gate.clk_en = 1;
+    dev->clk_gate.mst_clk_active = 1;
+    dev->clk_gate.mst_clk_sel = 1;
+
+    dev->dma_conf.val = 0;
+    // dev->dma_conf.tx_seg_trans_clr_en = 1;
+    // dev->dma_conf.rx_seg_trans_clr_en = 1;
+    // dev->dma_conf.dma_seg_trans_en = 0;
+}
+
+/**
+ * Check whether the previous operation is done.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if last command is done, otherwise false.
+ */
+static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
+{
+    return (dev->cmd.usr == 0);
+}
+
+/**
+ * Get the read data from the buffer after ``gpspi_flash_ll_read`` is done.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer to hold the output data
+ * @param read_len Length to get out of the buffer
+ */
+static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
+{
+    // if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
+    //     // If everything is word-aligned, do a faster memcpy
+    //     memcpy(buffer, (void *)dev->data_buf, read_len);
+    // } else {
+    //     // Otherwise, slow(er) path copies word by word
+    //     int copy_len = read_len;
+    //     for (int i = 0; i < (read_len + 3) / 4; i++) {
+    //         int word_len = MIN(sizeof(uint32_t), copy_len);
+    //         uint32_t word = dev->data_buf[i];
+    //         memcpy(buffer, &word, word_len);
+    //         buffer = (void *)((intptr_t)buffer + word_len);
+    //         copy_len -= word_len;
+    //     }
+    // }
+}
+
+/**
+ * Write a word to the data buffer.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param word Data to write at address 0.
+ */
+static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
+{
+    // dev->data_buf[0] = word;
+}
+
+/**
+ * Set the data to be written in the data buffer.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer holding the data
+ * @param length Length of data in bytes.
+ */
+static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length)
+{
+    // Load data registers, word at a time
+    // int num_words = (length + 3) / 4;
+    // for (int i = 0; i < num_words; i++) {
+    //     uint32_t word = 0;
+    //     uint32_t word_len = MIN(length, sizeof(word));
+    //     memcpy(&word, buffer, word_len);
+    //     dev->data_buf[i] = word;
+    //     length -= word_len;
+    //     buffer = (void *)((intptr_t)buffer + word_len);
+    // }
+}
+
+/**
+ * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases,
+ * should be configured before this is called.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void gpspi_flash_ll_user_start(spi_dev_t *dev)
+{
+    dev->cmd.update = 1;
+    while (dev->cmd.update);
+    dev->cmd.usr = 1;
+}
+
+/**
+ * Set HD pin high when flash work at spi mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
+{
+    dev->ctrl.hold_pol = pol_val;
+}
+
+/**
+ * Check whether the host is idle to perform new commands.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if the host is idle, otherwise false
+ */
+static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
+{
+    return dev->cmd.usr == 0;
+}
+
+/**
+ * Set phases for user-defined transaction to read
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
+{
+    typeof (dev->user) user = {
+        .usr_command = 1,
+        .usr_mosi = 0,
+        .usr_miso = 1,
+        .usr_addr = 1,
+    };
+    dev->user = user;
+}
+/*------------------------------------------------------------------------------
+ * Configs
+ *----------------------------------------------------------------------------*/
+/**
+ * Select which pin to use for the flash
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
+ */
+static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
+{
+    dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
+    dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
+}
+
+/**
+ * Set the read io mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param read_mode I/O mode to use in the following transactions.
+ */
+static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
+{
+    typeof (dev->ctrl) ctrl = dev->ctrl;
+    typeof (dev->user) user = dev->user;
+
+    ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
+    user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
+
+    switch (read_mode) {
+    case SPI_FLASH_FASTRD:
+        //the default option
+    case SPI_FLASH_SLOWRD:
+        break;
+    case SPI_FLASH_QIO:
+        ctrl.fread_quad = 1;
+        ctrl.faddr_quad = 1;
+        user.fwrite_quad = 1;
+        break;
+    case SPI_FLASH_QOUT:
+        ctrl.fread_quad = 1;
+        user.fwrite_quad = 1;
+        break;
+    case SPI_FLASH_DIO:
+        ctrl.fread_dual = 1;
+        ctrl.faddr_dual = 1;
+        user.fwrite_dual = 1;
+        break;
+    case SPI_FLASH_DOUT:
+        ctrl.fread_dual = 1;
+        user.fwrite_dual = 1;
+        break;
+    default:
+        abort();
+    }
+
+    dev->ctrl = ctrl;
+    dev->user = user;
+}
+
+/**
+ * Set clock frequency to work at.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param clock_val pointer to the clock value to set
+ */
+static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val)
+{
+    dev->clock.val = *clock_val;
+}
+
+/**
+ * Set the input length, in bits.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of input, in bits.
+ */
+static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
+{
+    dev->user.usr_miso = bitlen > 0;
+    if (bitlen) {
+        dev->ms_dlen.ms_data_bitlen = bitlen - 1;
+    }
+}
+
+/**
+ * Set the output length, in bits (not including command, address and dummy
+ * phases)
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of output, in bits.
+ */
+static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
+{
+    dev->user.usr_mosi = bitlen > 0;
+    if (bitlen) {
+        dev->ms_dlen.ms_data_bitlen = bitlen - 1;
+    }
+}
+
+/**
+ * Set the command.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param command Command to send
+ * @param bitlen Length of the command
+ */
+static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen)
+{
+    dev->user.usr_command = 1;
+    typeof(dev->user2) user2 = {
+        .usr_command_value = command,
+        .usr_command_bitlen = (bitlen - 1),
+    };
+    dev->user2 = user2;
+}
+
+/**
+ * Get the address length that is set in register, in bits.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ */
+static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev)
+{
+    return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
+}
+
+/**
+ * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of the address, in bits
+ */
+static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
+{
+    dev->user1.usr_addr_bitlen = (bitlen - 1);
+    dev->user.usr_addr = bitlen ? 1 : 0;
+}
+
+/**
+ * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param addr Address to send
+ */
+static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
+{
+    // The blank region should be all ones
+    // uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen);
+    // dev->addr = (addr << (32 - bitlen)) | padding_ones;
+}
+
+/**
+ * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param addr Address to send
+ */
+static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
+{
+    // dev->addr = addr;
+}
+
+/**
+ * Set the length of dummy cycles.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param dummy_n Cycles of dummy phases
+ */
+static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
+{
+    dev->user.usr_dummy = dummy_n ? 1 : 0;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
+}
+
+/**
+ * Set D/Q output level during dummy phase
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param out_en whether to enable IO output for dummy phase
+ * @param out_level dummy output level
+ */
+static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, uint32_t out_lev)
+{
+    dev->ctrl.dummy_out = out_en;
+    dev->ctrl.q_pol = out_lev;
+    dev->ctrl.d_pol = out_lev;
+}
+
+/**
+ * Set extra hold time of CS after the clocks.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param hold_n Cycles of clocks before CS is inactive
+ */
+static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
+{
+    dev->user1.cs_hold_time = hold_n - 1;
+    dev->user.cs_hold = (hold_n > 0? 1: 0);
+}
+
+static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
+{
+    dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    dev->user1.cs_setup_time = cs_setup_time - 1;
+}
+
+/**
+ * Calculate spi_flash clock frequency division parameters for register.
+ *
+ * @param clkdiv frequency division factor
+ *
+ * @return Register setting for the given clock division factor.
+ */
+static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
+{
+    uint32_t div_parameter;
+    // See comments of `clock` in `spi_struct.h`
+    if (clkdiv == 1) {
+        div_parameter = (1 << 31);
+    } else {
+        div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12));
+    }
+    return div_parameter;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/lpwdt_ll.h

@@ -0,0 +1,296 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for Timer Group register operations.
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "hal/misc.h"
+#include "hal/wdt_types.h"
+#include "soc/rtc_cntl_periph.h"
+#include "soc/efuse_reg.h"
+#include "esp_attr.h"
+
+#include "esp32h2/rom/ets_sys.h"
+
+/**
+ * @brief Enable the RWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
+{
+    // hw->config0.en = 1;
+}
+
+/**
+ * @brief Disable the RWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @note This function does not disable the flashboot mode. Therefore, given that
+ *       the MWDT is disabled using this function, a timeout can still occur
+ *       if the flashboot mode is simultaneously enabled.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
+{
+    // hw->config0.en = 0;
+}
+
+/**
+ * @brief Check if the RWDT is enabled
+ *
+ * @param hw Start address of the peripheral registers.
+ * @return True if RTC WDT is enabled
+ */
+FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
+{
+    return false;//(hw->config0.en) ? true : false;
+}
+
+/**
+ * @brief Configure a particular stage of the RWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param stage Which stage to configure
+ * @param timeout Number of timer ticks for the stage to timeout (see note).
+ * @param behavior What action to take when the stage times out
+ *
+ * @note The value of of RWDT stage 0 timeout register is special, in
+ *       that an implicit multiplier is applied to that value to produce
+ *       and effective timeout tick value. The multiplier is dependent
+ *       on an EFuse value. Therefore, when configuring stage 0, the valid
+ *       values for the timeout argument are:
+ *       - If Efuse value is 0, any even number between [2,2*UINT32_MAX]
+ *       - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX]
+ *       - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX]
+ *       - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX]
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
+{
+    // switch (stage) {
+    // case WDT_STAGE0:
+    //     hw->config0.stg0 = behavior;
+    //     //Account of implicty multiplier applied to stage 0 timeout tick config value
+    //     hw->config1 = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
+    //     break;
+    // case WDT_STAGE1:
+    //     hw->config0.stg1 = behavior;
+    //     hw->config2 = timeout_ticks;
+    //     break;
+    // case WDT_STAGE2:
+    //     hw->config0.stg2 = behavior;
+    //     hw->config3 = timeout_ticks;
+    //     break;
+    // case WDT_STAGE3:
+    //     hw->config0.stg3 = behavior;
+    //     hw->config4 = timeout_ticks;
+    //     break;
+    // default:
+    //     abort();
+    // }
+}
+
+/**
+ * @brief Disable a particular stage of the RWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param stage Which stage to disable
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage)
+{
+    // switch (stage) {
+    // case WDT_STAGE0:
+    //     hw->config0.stg0 = WDT_STAGE_ACTION_OFF;
+    //     break;
+    // case WDT_STAGE1:
+    //     hw->config0.stg1 = WDT_STAGE_ACTION_OFF;
+    //     break;
+    // case WDT_STAGE2:
+    //     hw->config0.stg2 = WDT_STAGE_ACTION_OFF;
+    //     break;
+    // case WDT_STAGE3:
+    //     hw->config0.stg3 = WDT_STAGE_ACTION_OFF;
+    //     break;
+    // default:
+    //     abort();
+    // }
+}
+
+/**
+ * @brief Set the length of the CPU reset action
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param length Length of CPU reset signal
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
+{
+    // hw->config0.cpu_reset_length = length;
+}
+
+/**
+ * @brief Set the length of the system reset action
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param length Length of system reset signal
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
+{
+    // hw->config0.sys_reset_length = length;
+}
+
+/**
+ * @brief Enable/Disable the RWDT flashboot mode.
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
+ *
+ * @note Flashboot mode is independent and can trigger a WDT timeout event if the
+ *       WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled
+ *       on flashboot, and should be disabled by software when flashbooting completes.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
+{
+    // hw->config0.flashboot_mod_en = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable CPU0 to be reset, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable)
+{
+    // hw->config0.procpu_reset_en = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable CPU1 to be reset, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
+{
+    // hw->config0.appcpu_reset_en = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Enable/Disable the RWDT pause during sleep functionality
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable)
+{
+    // hw->config0.pause_in_slp = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Enable/Disable chip reset on RWDT timeout.
+ *
+ * A chip reset also resets the analog portion of the chip. It will appear as a
+ * POWERON reset rather than an RTC reset.
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable)
+{
+    // hw->config5.chip_reset_en = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Set width of chip reset signal
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width)
+{
+    // ESP32H2-TODO: IDF-6402
+    // HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, chip_reset_width, width);
+}
+
+/**
+ * @brief Feed the RWDT
+ *
+ * Resets the current timer count and current stage.
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
+{
+    // ESP32H2-TODO: IDF-6402
+    // hw->feed.rtc_wdt_feed = 1;
+}
+
+/**
+ * @brief Enable write protection of the RWDT registers
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
+{
+    // ESP32H2-TODO: IDF-6402
+    // hw->wprotect = 0;
+}
+
+/**
+ * @brief Disable write protection of the RWDT registers
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
+{
+    // ESP32H2-TODO: IDF-6402
+    // hw->wprotect = RTC_CNTL_WDT_WKEY_VALUE;
+}
+
+/**
+ * @brief Enable the RWDT interrupt.
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param enable True to enable RWDT interrupt, false to disable.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
+{
+    // ESP32H2-TODO: IDF-6402
+    // hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
+}
+
+/**
+ * @brief Check if the RWDT interrupt has been triggered
+ *
+ * @param hw Start address of the peripheral registers.
+ * @return True if the RWDT interrupt was triggered
+ */
+FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
+{
+    return false;//(hw->int_st.lp_wdt_int_st) ? true : false; // ESP32H2-TODO: IDF-6402
+}
+
+/**
+ * @brief Clear the RWDT interrupt status.
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw)
+{
+    // ESP32H2-TODO: IDF-6402
+    // hw->int_clr.lp_wdt_int_clr = 1;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/mmu_ll.h

@@ -0,0 +1,255 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for MMU register operations
+
+#pragma once
+
+#include "soc/spi_mem_reg.h"
+#include "soc/ext_mem_defs.h"
+#include "hal/assert.h"
+#include "hal/mmu_types.h"
+#include "hal/efuse_ll.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief The real MMU page size get from Kconfig.
+ *
+ * @note Only used in this file
+ */
+#define MMU_LL_PAGE_SIZE                   (CONFIG_MMU_PAGE_SIZE)
+
+__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
+{
+    unsigned cnt = efuse_ll_get_flash_crypt_cnt();
+    // 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
+    cnt = ((cnt >> 2) ^ (cnt >> 1) ^ cnt) & 0x1;
+    return (cnt == 1);
+}
+
+
+/**
+ * Get MMU page size
+ *
+ * @param mmu_id  MMU ID
+ *
+ * @return MMU page size code
+ */
+__attribute__((always_inline))
+static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
+{
+    (void)mmu_id;
+     uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE);
+    return  (page_size_code == 0) ? MMU_PAGE_64KB : \
+            (page_size_code == 1) ? MMU_PAGE_32KB : \
+            (page_size_code == 2) ? MMU_PAGE_16KB : \
+            MMU_PAGE_8KB;
+}
+
+/**
+ * Set MMU page size
+ *
+ * @param size  MMU page size
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
+{
+    uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 : \
+                      (size == MMU_PAGE_32KB) ? 1 : \
+                      (size == MMU_PAGE_16KB) ? 2 : \
+                      (size == MMU_PAGE_8KB) ? 3 : 0;
+    REG_SET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MEM_MMU_PAGE_SIZE, reg_val);
+}
+
+/**
+ * Check if the external memory vaddr region is valid
+ *
+ * @param mmu_id      MMU ID
+ * @param vaddr_start start of the virtual address
+ * @param len         length, in bytes
+ *
+ * @return
+ *         True for valid
+ */
+__attribute__((always_inline))
+static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len)
+{
+    (void)mmu_id;
+    uint32_t vaddr_end = vaddr_start + len;
+    return (ADDRESS_IN_IRAM0_CACHE(vaddr_start, MMU_LL_PAGE_SIZE) && ADDRESS_IN_IRAM0_CACHE(vaddr_end, MMU_LL_PAGE_SIZE)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start, MMU_LL_PAGE_SIZE) && ADDRESS_IN_DRAM0_CACHE(vaddr_end, MMU_LL_PAGE_SIZE));
+}
+
+/**
+ * To get the MMU table entry id to be mapped
+ *
+ * @param mmu_id  MMU ID
+ * @param vaddr   virtual address to be mapped
+ *
+ * @return
+ *         MMU table entry id
+ */
+__attribute__((always_inline))
+static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
+{
+    (void)mmu_id;
+
+    mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
+    uint32_t shift_code = 0;
+    switch (page_size) {
+        case MMU_PAGE_64KB:
+            shift_code = 16;
+            break;
+        case MMU_PAGE_32KB:
+            shift_code = 15;
+            break;
+        case MMU_PAGE_16KB:
+            shift_code = 14;
+            break;
+        case MMU_PAGE_8KB:
+            shift_code = 13;
+            break;
+        default:
+            HAL_ASSERT(shift_code);
+    }
+
+    return ((vaddr & MMU_VADDR_MASK(page_size)) >> shift_code);
+}
+
+/**
+ * Format the paddr to be mappable
+ *
+ * @param mmu_id  MMU ID
+ * @param paddr   physical address to be mapped
+ *
+ * @return
+ *         mmu_val - paddr in MMU table supported format
+ */
+__attribute__((always_inline))
+static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr)
+{
+    (void)mmu_id;
+
+    mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
+    uint32_t shift_code = 0;
+    switch (page_size) {
+        case MMU_PAGE_64KB:
+            shift_code = 16;
+            break;
+        case MMU_PAGE_32KB:
+            shift_code = 15;
+            break;
+        case MMU_PAGE_16KB:
+            shift_code = 14;
+            break;
+        case MMU_PAGE_8KB:
+            shift_code = 13;
+            break;
+        default:
+            HAL_ASSERT(shift_code);
+    }
+
+    return paddr >> shift_code;
+}
+
+/**
+ * Write to the MMU table to map the virtual memory and the physical memory
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ * @param mmu_val  Value to be set into an MMU entry, for physical address
+ * @param target   MMU target physical memory.
+ */
+__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, uint32_t target)
+{
+    (void)mmu_id;
+    (void)target;
+    uint32_t mmu_raw_value;
+    if (mmu_ll_cache_encryption_enabled()) {
+        mmu_val |= MMU_SENSITIVE;
+    }
+    /* Note: for ESP32-H2, invert invalid bit for compatible with upper-layer software */
+    mmu_raw_value = mmu_val ^ MMU_INVALID_MASK;
+    REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
+    REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
+}
+
+/**
+ * Read the raw value from MMU table
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ * @param mmu_val  Value to be read from MMU table
+ */
+__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+
+    uint32_t mmu_raw_value;
+    uint32_t ret;
+    REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
+    mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
+    if (mmu_ll_cache_encryption_enabled()) {
+        mmu_raw_value &= ~MMU_SENSITIVE;
+    }
+    /* Note: for ESP32-H2, invert invalid bit for compatible with upper-layer software */
+    ret = mmu_raw_value ^ MMU_INVALID_MASK;
+    return ret;
+}
+
+/**
+ * Set MMU table entry as invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry
+ */
+__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+
+    REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
+    REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), MMU_INVALID);
+}
+
+/**
+ * Get MMU table entry is invalid
+ *
+ * @param mmu_id   MMU ID
+ * @param entry_id MMU entry ID
+ * return ture for MMU entry is invalid, false for valid
+ */
+__attribute__((always_inline)) static inline bool mmu_ll_get_entry_is_invalid(uint32_t mmu_id, uint32_t entry_id)
+{
+    (void)mmu_id;
+
+    uint32_t mmu_raw_value;
+    REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
+    mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
+    /* Note: for ESP32-H2, the invalid-bit of MMU: 0 for invalid, 1 for valid */
+    return (mmu_raw_value & MMU_INVALID_MASK) ? false : true;
+}
+
+#ifdef __cplusplus
+}
+
+#endif
+
+
+/**
+ * Unmap all the items in the MMU table
+ *
+ * @param mmu_id MMU ID
+ */
+__attribute__((always_inline))
+static inline void mmu_ll_unmap_all(uint32_t mmu_id)
+{
+    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+        mmu_ll_set_entry_invalid(mmu_id, i);
+    }
+}

components/hal/esp32h2/include/hal/mpu_ll.h

@@ -0,0 +1,45 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+
+#include "soc/soc_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* This LL is currently unused for ESP32-H2 - cleanup is TODO ESP32-H2 IDF-2375 */
+
+static inline uint32_t mpu_ll_id_to_addr(unsigned id)
+{
+    abort();
+}
+
+static inline void mpu_ll_set_region_rw(uint32_t addr)
+{
+    abort();
+}
+
+static inline void mpu_ll_set_region_rwx(uint32_t addr)
+{
+    abort();
+}
+
+static inline void mpu_ll_set_region_x(uint32_t addr)
+{
+    abort();
+}
+
+
+static inline void mpu_ll_set_region_illegal(uint32_t addr)
+{
+    abort();
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/mwdt_ll.h

@@ -0,0 +1,253 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for Timer Group register operations.
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/timer_periph.h"
+#include "soc/timer_group_struct.h"
+#include "hal/wdt_types.h"
+#include "hal/assert.h"
+#include "esp_attr.h"
+#include "hal/misc.h"
+
+//Type check wdt_stage_action_t
+_Static_assert(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+_Static_assert(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+_Static_assert(WDT_STAGE_ACTION_RESET_CPU == TIMG_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+_Static_assert(WDT_STAGE_ACTION_RESET_SYSTEM == TIMG_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
+//Type check wdt_reset_sig_length_t
+_Static_assert(WDT_RESET_SIG_LENGTH_100ns == TIMG_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_200ns == TIMG_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_300ns == TIMG_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_400ns == TIMG_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_500ns == TIMG_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_800ns == TIMG_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_1_6us == TIMG_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+_Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
+
+/**
+ * @brief Enable the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
+{
+    hw->wdtconfig0.wdt_en = 1;
+}
+
+/**
+ * @brief Disable the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @note This function does not disable the flashboot mode. Therefore, given that
+ *       the MWDT is disabled using this function, a timeout can still occur
+ *       if the flashboot mode is simultaneously enabled.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
+{
+    hw->wdtconfig0.wdt_en = 0;
+}
+
+/**
+ * Check if the MWDT is enabled
+ *
+ * @param hw Start address of the peripheral registers.
+ * @return True if the MWDT is enabled, false otherwise
+ */
+FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
+{
+    return (hw->wdtconfig0.wdt_en) ? true : false;
+}
+
+/**
+ * @brief Configure a particular stage of the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param stage Which stage to configure
+ * @param timeout Number of timer ticks for the stage to timeout
+ * @param behavior What action to take when the stage times out
+ */
+FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior)
+{
+    switch (stage) {
+    case WDT_STAGE0:
+        hw->wdtconfig0.wdt_stg0 = behavior;
+        hw->wdtconfig2.wdt_stg0_hold = timeout;
+        break;
+    case WDT_STAGE1:
+        hw->wdtconfig0.wdt_stg1 = behavior;
+        hw->wdtconfig3.wdt_stg1_hold = timeout;
+        break;
+    case WDT_STAGE2:
+        hw->wdtconfig0.wdt_stg2 = behavior;
+        hw->wdtconfig4.wdt_stg2_hold = timeout;
+        break;
+    case WDT_STAGE3:
+        hw->wdtconfig0.wdt_stg3 = behavior;
+        hw->wdtconfig5.wdt_stg3_hold = timeout;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported WDT stage");
+        break;
+    }
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Disable a particular stage of the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param stage Which stage to disable
+ */
+FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
+{
+    switch (stage) {
+    case WDT_STAGE0:
+        hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE1:
+        hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE2:
+        hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE3:
+        hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported WDT stage");
+        break;
+    }
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Set the length of the CPU reset action
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param length Length of CPU reset signal
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
+{
+    hw->wdtconfig0.wdt_cpu_reset_length = length;
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Set the length of the system reset action
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param length Length of system reset signal
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
+{
+    hw->wdtconfig0.wdt_sys_reset_length = length;
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Enable/Disable the MWDT flashboot mode.
+ *
+ * @param hw Beginning address of the peripheral registers.
+ * @param enable True to enable WDT flashboot mode, false to disable WDT flashboot mode.
+ *
+ * @note Flashboot mode is independent and can trigger a WDT timeout event if the
+ *       WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled
+ *       on flashboot, and should be disabled by software when flashbooting completes.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
+{
+    hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Set the clock prescaler of the MWDT
+ *
+ * @param hw Start address of the peripheral registers.
+ * @param prescaler Prescaler value between 1 to 65535
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
+{
+    // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
+    // We take care of the "read-modify-write" procedure by ourselves.
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler);
+    //Config registers are updated asynchronously
+    hw->wdtconfig0.wdt_conf_update_en = 1;
+}
+
+/**
+ * @brief Feed the MWDT
+ *
+ * Resets the current timer count and current stage.
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
+{
+    hw->wdtfeed.wdt_feed = 1;
+}
+
+/**
+ * @brief Enable write protection of the MWDT registers
+ *
+ * Locking the MWDT will prevent any of the MWDT's registers from being modified
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
+{
+    hw->wdtwprotect.wdt_wkey = 0;
+}
+
+/**
+ * @brief Disable write protection of the MWDT registers
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
+{
+    hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
+}
+
+/**
+ * @brief Clear the MWDT interrupt status.
+ *
+ * @param hw Start address of the peripheral registers.
+ */
+FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
+{
+    hw->int_clr_timers.wdt_int_clr = 1;
+}
+
+/**
+ * @brief Set the interrupt enable bit for the MWDT interrupt.
+ *
+ * @param hw Beginning address of the peripheral registers.
+ * @param enable Whether to enable the MWDT interrupt
+ */
+FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
+{
+    hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h

@@ -0,0 +1,62 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/regi2c_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Reset (Disable) the I2C internal bus for all regi2c registers
+ */
+static inline void regi2c_ctrl_ll_i2c_reset(void)
+{
+    SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
+}
+
+/**
+ * @brief Enable the I2C internal bus to do I2C read/write operation to the BBPLL configuration register
+ */
+static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void)
+{
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M);
+}
+
+/**
+ * @brief Start BBPLL self-calibration
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
+{
+    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+}
+
+/**
+ * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
+ */
+static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
+{
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
+}
+
+/**
+ * @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
+ */
+static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
+{
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/rtc_cntl_ll.h

@@ -0,0 +1,70 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+#include "soc/rtc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_pins(void)
+{
+    return 0;
+    // ESP32H2-TODO: IDF-6401
+}
+
+static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
+{
+    // ESP32H2-TODO: IDF-6401
+    return 0;
+}
+
+static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void)
+{
+    // ESP32H2-TODO: IDF-6401
+}
+
+static inline void rtc_cntl_ll_gpio_set_wakeup_pins(void)
+{
+    // ESP32H2-TODO: IDF-5718
+}
+
+static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void)
+{
+    // ESP32H2-TODO: IDF-5718
+}
+
+static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr)
+{
+    // ESP32H2-TODO: IDF-5718 has removed the retention feature
+}
+
+static inline void rtc_cntl_ll_enable_cpu_retention_clock(void)
+{
+    // ESP32H2-TODO: IDF-5718 has removed the retention feature
+}
+
+static inline void rtc_cntl_ll_enable_cpu_retention(void)
+{
+    // ESP32H2-TODO: IDF-5718 has removed the retention feature
+}
+
+static inline void rtc_cntl_ll_disable_cpu_retention(void)
+{
+    // ESP32H2-TODO: IDF-5718 has removed the retention feature
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/rwdt_ll.h

@@ -0,0 +1,77 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// The LL layer for Timer Group register operations.
+// Note that most of the register operations in this layer are non-atomic operations.
+
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "hal/lpwdt_ll.h"
+
+#define rwdt_ll_enable(hw) \
+        lpwdt_ll_enable(hw)
+
+#define rwdt_ll_disable(hw) \
+        lpwdt_ll_disable(hw)
+
+#define rwdt_ll_check_if_enabled(hw) \
+        lpwdt_ll_check_if_enabled(hw)
+
+#define rwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) \
+        lpwdt_ll_config_stage(hw, stage, timeout_ticks, behavior)
+
+#define rwdt_ll_disable_stage(hw, stage) \
+        lpwdt_ll_disable_stage(hw, stage)
+
+#define rwdt_ll_set_cpu_reset_length(hw, length) \
+        lpwdt_ll_set_cpu_reset_length(hw, length)
+
+#define rwdt_ll_set_sys_reset_length(hw, length) \
+        lpwdt_ll_set_sys_reset_length(hw, length)
+
+#define rwdt_ll_set_flashboot_en(hw, enable) \
+        lpwdt_ll_set_flashboot_en(hw, enable)
+
+#define rwdt_ll_set_procpu_reset_en(hw, enable) \
+        lpwdt_ll_set_procpu_reset_en(hw, enable)
+
+#define rwdt_ll_set_appcpu_reset_en(hw, enable) \
+        lpwdt_ll_set_appcpu_reset_en(hw, enable)
+
+#define rwdt_ll_set_pause_in_sleep_en(hw, enable) \
+        lpwdt_ll_set_pause_in_sleep_en(hw, enable)
+
+#define rwdt_ll_set_chip_reset_en(hw, enable) \
+        lpwdt_ll_set_chip_reset_en(hw, enable)
+
+#define rwdt_ll_set_chip_reset_width(hw, width) \
+        lpwdt_ll_set_chip_reset_width(hw, width)
+
+#define rwdt_ll_feed(hw) \
+        lpwdt_ll_feed(hw)
+
+#define rwdt_ll_write_protect_enable(hw) \
+        lpwdt_ll_write_protect_enable(hw)
+
+#define rwdt_ll_write_protect_disable(hw) \
+        lpwdt_ll_write_protect_disable(hw)
+
+#define rwdt_ll_set_intr_enable(hw, enable) \
+        lpwdt_ll_set_intr_enable(hw, enable)
+
+#define rwdt_ll_check_intr_status(hw) \
+        lpwdt_ll_check_intr_status(hw)
+
+#define rwdt_ll_clear_intr_status(hw) \
+        lpwdt_ll_clear_intr_status(hw)
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h

@@ -0,0 +1,149 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+// The Lowlevel layer for SPI Flash Encryption.
+
+#include <stdbool.h>
+#include <string.h>
+#include "soc/hp_system_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/soc.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// Choose type of chip you want to encrypt manully
+typedef enum
+{
+    FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
+    PSRAM_ENCRYPTION_MANU = 1  ///!< Manually encrypt the psram chip.
+} flash_encrypt_ll_type_t;
+
+/**
+ * Enable the flash encryption function under spi boot mode and download boot mode.
+ */
+static inline void spi_flash_encrypt_ll_enable(void)
+{
+    // REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
+    //             HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
+    //             HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
+}
+
+/*
+ * Disable the flash encryption mode.
+ */
+static inline void spi_flash_encrypt_ll_disable(void)
+{
+    // REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
+    //             HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
+}
+
+/**
+ * Choose type of chip you want to encrypt manully
+ *
+ * @param type The type of chip to be encrypted
+ *
+ * @note The hardware currently support flash encryption.
+ */
+static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
+{
+    // Our hardware only support flash encryption
+    // HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
+    // REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_XTS_DESTINATION, type);
+}
+
+/**
+ * Configure the data size of a single encryption.
+ *
+ * @param block_size Size of the desired block.
+ */
+static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
+{
+    // Desired block should not be larger than the block size.
+    // REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_XTS_LINESIZE, size >> 5);
+}
+
+/**
+ * Save 32-bit piece of plaintext.
+ *
+ * @param address the address of written flash partition.
+ * @param buffer Buffer to store the input data.
+ * @param size Buffer size.
+ *
+ */
+static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
+{
+    // uint32_t plaintext_offs = (address % 64);
+    // memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
+}
+
+/**
+ * Copy the flash address to XTS_AES physical address
+ *
+ * @param flash_addr flash address to write.
+ */
+static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
+{
+    // REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_XTS_PHYSICAL_ADDRESS, flash_addr);
+}
+
+/**
+ * Start flash encryption
+ */
+static inline void spi_flash_encrypt_ll_calculate_start(void)
+{
+    // REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_XTS_TRIGGER, 1);
+}
+
+/**
+ * Wait for flash encryption termination
+ */
+static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
+{
+    // while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) == 0x1) {
+    // }
+}
+
+/**
+ * Finish the flash encryption and make encrypted result accessible to SPI.
+ */
+static inline void spi_flash_encrypt_ll_done(void)
+{
+    // REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_XTS_RELEASE);
+    // while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_XTS_STATE) != 0x3) {
+    // }
+}
+
+/**
+ * Set to destroy encrypted result
+ */
+static inline void spi_flash_encrypt_ll_destroy(void)
+{
+    // REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_XTS_DESTROY);
+}
+
+/**
+ * Check if is qualified to encrypt the buffer
+ *
+ * @param address the address of written flash partition.
+ * @param length Buffer size.
+ */
+static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
+{
+    return false;//((address % length) == 0) ? true : false;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/spi_flash_ll.h

@@ -0,0 +1,100 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in soc/include/hal/readme.md
+ ******************************************************************************/
+
+// The Lowlevel layer for SPI Flash
+
+#pragma once
+
+#include "gpspi_flash_ll.h"
+#include "spimem_flash_ll.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
+                                            : gpspi_flash_ll_calculate_clock_reg(clock_div))
+
+#define spi_flash_ll_get_source_clock_freq_mhz(host_id)  (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ)
+
+#define spi_flash_ll_get_hw(host_id)  (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \
+                                      : gpspi_flash_ll_get_hw(host_id)))
+
+#define spi_flash_ll_hw_get_id(dev) ({int dev_id = spimem_flash_ll_hw_get_id(dev); \
+                                     if (dev_id < 0) {\
+                                        dev_id = gpspi_flash_ll_hw_get_id(dev);\
+                                     }\
+                                     dev_id; \
+                                    })
+// Since ESP32-H2, WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
+#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS  (8)
+
+typedef union  {
+    gpspi_flash_ll_clock_reg_t gpspi;
+    spimem_flash_ll_clock_reg_t spimem;
+} spi_flash_ll_clock_reg_t;
+
+#ifdef GPSPI_BUILD
+#define spi_flash_ll_reset(dev)                              gpspi_flash_ll_reset((spi_dev_t*)dev)
+#define spi_flash_ll_cmd_is_done(dev)                        gpspi_flash_ll_cmd_is_done((spi_dev_t*)dev)
+#define spi_flash_ll_get_buffer_data(dev, buffer, read_len)  gpspi_flash_ll_get_buffer_data((spi_dev_t*)dev, buffer, read_len)
+#define spi_flash_ll_set_buffer_data(dev, buffer, len)       gpspi_flash_ll_set_buffer_data((spi_dev_t*)dev, buffer, len)
+#define spi_flash_ll_user_start(dev)                         gpspi_flash_ll_user_start((spi_dev_t*)dev)
+#define spi_flash_ll_host_idle(dev)                          gpspi_flash_ll_host_idle((spi_dev_t*)dev)
+#define spi_flash_ll_read_phase(dev)                         gpspi_flash_ll_read_phase((spi_dev_t*)dev)
+#define spi_flash_ll_set_cs_pin(dev, pin)                    gpspi_flash_ll_set_cs_pin((spi_dev_t*)dev, pin)
+#define spi_flash_ll_set_read_mode(dev, read_mode)           gpspi_flash_ll_set_read_mode((spi_dev_t*)dev, read_mode)
+#define spi_flash_ll_set_clock(dev, clk)                     gpspi_flash_ll_set_clock((spi_dev_t*)dev, (gpspi_flash_ll_clock_reg_t*)clk)
+#define spi_flash_ll_set_miso_bitlen(dev, bitlen)            gpspi_flash_ll_set_miso_bitlen((spi_dev_t*)dev, bitlen)
+#define spi_flash_ll_set_mosi_bitlen(dev, bitlen)            gpspi_flash_ll_set_mosi_bitlen((spi_dev_t*)dev, bitlen)
+#define spi_flash_ll_set_command(dev, cmd, bitlen)           gpspi_flash_ll_set_command((spi_dev_t*)dev, cmd, bitlen)
+#define spi_flash_ll_set_addr_bitlen(dev, bitlen)            gpspi_flash_ll_set_addr_bitlen((spi_dev_t*)dev, bitlen)
+#define spi_flash_ll_get_addr_bitlen(dev)                    gpspi_flash_ll_get_addr_bitlen((spi_dev_t*)dev)
+#define spi_flash_ll_set_address(dev, addr)                  gpspi_flash_ll_set_address((spi_dev_t*)dev, addr)
+#define spi_flash_ll_set_usr_address(dev, addr, bitlen)      gpspi_flash_ll_set_usr_address((spi_dev_t*)dev, addr, bitlen)
+#define spi_flash_ll_set_dummy(dev, dummy)                   gpspi_flash_ll_set_dummy((spi_dev_t*)dev, dummy)
+#define spi_flash_ll_set_hold(dev, hold_n)                   gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n)
+#define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
+#define spi_flash_ll_set_extra_address(dev, extra_addr)      { /* Not supported on gpspi on ESP32-H2*/ }
+#else
+#define spi_flash_ll_reset(dev)                              spimem_flash_ll_reset((spi_mem_dev_t*)dev)
+#define spi_flash_ll_cmd_is_done(dev)                        spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
+#define spi_flash_ll_erase_chip(dev)                         spimem_flash_ll_erase_chip((spi_mem_dev_t*)dev)
+#define spi_flash_ll_erase_sector(dev)                       spimem_flash_ll_erase_sector((spi_mem_dev_t*)dev)
+#define spi_flash_ll_erase_block(dev)                        spimem_flash_ll_erase_block((spi_mem_dev_t*)dev)
+#define spi_flash_ll_set_write_protect(dev, wp)              spimem_flash_ll_set_write_protect((spi_mem_dev_t*)dev, wp)
+#define spi_flash_ll_get_buffer_data(dev, buffer, read_len)  spimem_flash_ll_get_buffer_data((spi_mem_dev_t*)dev, buffer, read_len)
+#define spi_flash_ll_set_buffer_data(dev, buffer, len)       spimem_flash_ll_set_buffer_data((spi_mem_dev_t*)dev, buffer, len)
+#define spi_flash_ll_program_page(dev, buffer, len)          spimem_flash_ll_program_page((spi_mem_dev_t*)dev, buffer, len)
+#define spi_flash_ll_user_start(dev)                         spimem_flash_ll_user_start((spi_mem_dev_t*)dev)
+#define spi_flash_ll_host_idle(dev)                          spimem_flash_ll_host_idle((spi_mem_dev_t*)dev)
+#define spi_flash_ll_read_phase(dev)                         spimem_flash_ll_read_phase((spi_mem_dev_t*)dev)
+#define spi_flash_ll_set_cs_pin(dev, pin)                    spimem_flash_ll_set_cs_pin((spi_mem_dev_t*)dev, pin)
+#define spi_flash_ll_set_read_mode(dev, read_mode)           spimem_flash_ll_set_read_mode((spi_mem_dev_t*)dev, read_mode)
+#define spi_flash_ll_set_clock(dev, clk)                     spimem_flash_ll_set_clock((spi_mem_dev_t*)dev, (spimem_flash_ll_clock_reg_t*)clk)
+#define spi_flash_ll_set_miso_bitlen(dev, bitlen)            spimem_flash_ll_set_miso_bitlen((spi_mem_dev_t*)dev, bitlen)
+#define spi_flash_ll_set_mosi_bitlen(dev, bitlen)            spimem_flash_ll_set_mosi_bitlen((spi_mem_dev_t*)dev, bitlen)
+#define spi_flash_ll_set_command(dev, cmd, bitlen)           spimem_flash_ll_set_command((spi_mem_dev_t*)dev, cmd, bitlen)
+#define spi_flash_ll_set_addr_bitlen(dev, bitlen)            spimem_flash_ll_set_addr_bitlen((spi_mem_dev_t*)dev, bitlen)
+#define spi_flash_ll_get_addr_bitlen(dev)                    spimem_flash_ll_get_addr_bitlen((spi_mem_dev_t*) dev)
+#define spi_flash_ll_set_address(dev, addr)                  spimem_flash_ll_set_address((spi_mem_dev_t*)dev, addr)
+#define spi_flash_ll_set_usr_address(dev, addr, bitlen)      spimem_flash_ll_set_usr_address((spi_mem_dev_t*)dev, addr, bitlen)
+#define spi_flash_ll_set_dummy(dev, dummy)                   spimem_flash_ll_set_dummy((spi_mem_dev_t*)dev, dummy)
+#define spi_flash_ll_set_hold(dev, hold_n)                   spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n)
+#define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time)
+#define spi_flash_ll_set_extra_address(dev, extra_addr)      spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr)
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/spimem_flash_ll.h

@@ -0,0 +1,597 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in soc/include/hal/readme.md
+ ******************************************************************************/
+
+// The Lowlevel layer for SPI Flash
+
+#pragma once
+
+#include <stdlib.h>
+#include <sys/param.h> // For MIN/MAX
+#include <stdbool.h>
+#include <string.h>
+
+#include "soc/spi_periph.h"
+#include "soc/spi_mem_struct.h"
+#include "hal/assert.h"
+#include "hal/spi_types.h"
+#include "hal/spi_flash_types.h"
+#include "soc/pcr_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define spimem_flash_ll_get_hw(host_id)  (((host_id)==SPI1_HOST ?  &SPIMEM1 : NULL ))
+#define spimem_flash_ll_hw_get_id(dev)   ((dev) == (void*)&SPIMEM1? SPI1_HOST: -1)
+
+typedef typeof(SPIMEM1.clock.val) spimem_flash_ll_clock_reg_t;
+
+/*------------------------------------------------------------------------------
+ * Control
+ *----------------------------------------------------------------------------*/
+/**
+ * Reset peripheral registers before configuration and starting control
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
+{
+    dev->user.val = 0;
+    dev->ctrl.val = 0;
+}
+
+/**
+ * Check whether the previous operation is done.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if last command is done, otherwise false.
+ */
+static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
+{
+    return (dev->cmd.val == 0);
+}
+
+/**
+ * Erase the flash chip.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_erase_chip(spi_mem_dev_t *dev)
+{
+    dev->cmd.flash_ce = 1;
+}
+
+/**
+ * Erase the sector, the address should be set by spimem_flash_ll_set_address.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_erase_sector(spi_mem_dev_t *dev)
+{
+    dev->ctrl.val = 0;
+    dev->cmd.flash_se = 1;
+}
+
+/**
+ * Erase the block, the address should be set by spimem_flash_ll_set_address.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_erase_block(spi_mem_dev_t *dev)
+{
+    dev->cmd.flash_be = 1;
+}
+
+/**
+ * Suspend erase/program operation.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_suspend(spi_mem_dev_t *dev)
+{
+    dev->flash_sus_ctrl.flash_pes = 1;
+}
+
+/**
+ * Resume suspended erase/program operation.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_resume(spi_mem_dev_t *dev)
+{
+    dev->flash_sus_ctrl.flash_per = 1;
+}
+
+/**
+ * Initialize auto suspend mode, and esp32H2 doesn't support disable auto-suspend.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param auto_sus Enable/disable Flash Auto-Suspend.
+ */
+static inline void spimem_flash_ll_auto_suspend_init(spi_mem_dev_t *dev, bool auto_sus)
+{
+    dev->flash_sus_ctrl.flash_pes_en = auto_sus;
+}
+
+/**
+ * Initialize auto resume mode
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param auto_res Enable/Disable Flash Auto-Resume.
+ *
+ */
+static inline void spimem_flash_ll_auto_resume_init(spi_mem_dev_t *dev, bool auto_res)
+{
+    dev->flash_sus_ctrl.pes_per_en = auto_res;
+}
+
+/**
+ * Setup the flash suspend command, may vary from chips to chips.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param sus_cmd Flash suspend command.
+ *
+ */
+static inline void spimem_flash_ll_suspend_cmd_setup(spi_mem_dev_t *dev, uint32_t sus_cmd)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd);
+}
+
+/**
+ * Setup the flash resume command, may vary from chips to chips.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param res_cmd Flash resume command.
+ *
+ */
+static inline void spimem_flash_ll_resume_cmd_setup(spi_mem_dev_t *dev, uint32_t res_cmd)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->sus_status, flash_per_command, res_cmd);
+}
+
+/**
+ * Setup the flash read suspend status command, may vary from chips to chips.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param pesr_cmd Flash read suspend status command.
+ *
+ */
+static inline void spimem_flash_ll_rd_sus_cmd_setup(spi_mem_dev_t *dev, uint32_t pesr_cmd)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd);
+}
+
+/**
+ * Setup to check SUS/SUS1/SUS2 to ensure the suspend status of flashs.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param sus_check_sus_en 1: enable, 0: disable.
+ *
+ */
+static inline void spimem_flash_ll_sus_check_sus_setup(spi_mem_dev_t *dev, bool sus_check_sus_en)
+{
+    dev->flash_sus_ctrl.sus_timeout_cnt = 5;
+    dev->flash_sus_ctrl.pes_end_en = sus_check_sus_en;
+}
+
+/**
+ * Setup to check SUS/SUS1/SUS2 to ensure the resume status of flashs.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param sus_check_sus_en 1: enable, 0: disable.
+ *
+ */
+static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool res_check_sus_en)
+{
+    dev->flash_sus_ctrl.sus_timeout_cnt = 5;
+    dev->flash_sus_ctrl.per_end_en = res_check_sus_en;
+}
+
+/**
+ * Set 8 bit command to read suspend status
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf)
+{
+    dev->flash_sus_ctrl.frd_sus_2b = 0;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf);
+}
+
+/**
+ * Initialize auto wait idle mode
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param auto_waiti Enable/disable auto wait-idle function
+ */
+static inline void spimem_flash_ll_auto_wait_idle_init(spi_mem_dev_t *dev, bool auto_waiti)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05);
+    dev->flash_sus_ctrl.flash_per_wait_en = auto_waiti;
+    dev->flash_sus_ctrl.flash_pes_wait_en = auto_waiti;
+}
+
+/**
+ * Return the suspend status of erase or program operations.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if suspended, otherwise false.
+ */
+static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
+{
+    return dev->sus_status.flash_sus;
+}
+
+/**
+ * Enable/disable write protection for the flash chip.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param wp true to enable the protection, false to disable (write enable).
+ */
+static inline void spimem_flash_ll_set_write_protect(spi_mem_dev_t *dev, bool wp)
+{
+    if (wp) {
+        dev->cmd.flash_wrdi = 1;
+    } else {
+        dev->cmd.flash_wren = 1;
+    }
+}
+
+/**
+ * Get the read data from the buffer after ``spimem_flash_ll_read`` is done.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer to hold the output data
+ * @param read_len Length to get out of the buffer
+ */
+static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
+{
+    if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
+        // If everything is word-aligned, do a faster memcpy
+        memcpy(buffer, (void *)dev->data_buf, read_len);
+    } else {
+        // Otherwise, slow(er) path copies word by word
+        int copy_len = read_len;
+        for (int i = 0; i < (read_len + 3) / 4; i++) {
+            int word_len = MIN(sizeof(uint32_t), copy_len);
+            uint32_t word = dev->data_buf[i];
+            memcpy(buffer, &word, word_len);
+            buffer = (void *)((intptr_t)buffer + word_len);
+            copy_len -= word_len;
+        }
+    }
+}
+
+/**
+ * Set the data to be written in the data buffer.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer holding the data
+ * @param length Length of data in bytes.
+ */
+static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
+{
+    // Load data registers, word at a time
+    int num_words = (length + 3) / 4;
+    for (int i = 0; i < num_words; i++) {
+        uint32_t word = 0;
+        uint32_t word_len = MIN(length, sizeof(word));
+        memcpy(&word, buffer, word_len);
+        dev->data_buf[i] = word;
+        length -= word_len;
+        buffer = (void *)((intptr_t)buffer + word_len);
+    }
+}
+
+
+/**
+ * Program a page of the flash chip. Call ``spimem_flash_ll_set_address`` before
+ * this to set the address to program.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param buffer Buffer holding the data to program
+ * @param length Length to program.
+ */
+static inline void spimem_flash_ll_program_page(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
+{
+    dev->user.usr_dummy = 0;
+    spimem_flash_ll_set_buffer_data(dev, buffer, length);
+    dev->cmd.flash_pp = 1;
+}
+
+/**
+ * Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases,
+ * should be configured before this is called.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev)
+{
+    dev->cmd.usr = 1;
+}
+
+/**
+ * Check whether the host is idle to perform new commands.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ * @return true if the host is idle, otherwise false
+ */
+static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
+{
+    return dev->cmd.mst_st == 0;
+}
+
+/**
+ * Set phases for user-defined transaction to read
+ *
+ * @param dev Beginning address of the peripheral registers.
+ */
+static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
+{
+    typeof (dev->user) user = {
+        .usr_command = 1,
+        .usr_mosi = 0,
+        .usr_miso = 1,
+        .usr_addr = 1,
+    };
+    dev->user = user;
+}
+/*------------------------------------------------------------------------------
+ * Configs
+ *----------------------------------------------------------------------------*/
+/**
+ * Select which pin to use for the flash
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
+ */
+static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
+{
+    dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
+    dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
+}
+
+/**
+ * Set the read io mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param read_mode I/O mode to use in the following transactions.
+ */
+static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
+{
+    typeof (dev->ctrl) ctrl = dev->ctrl;
+    ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
+    ctrl.val |= SPI_MEM_FASTRD_MODE_M;
+    switch (read_mode) {
+    case SPI_FLASH_FASTRD:
+        //the default option
+        break;
+    case SPI_FLASH_QIO:
+        ctrl.fread_qio = 1;
+        break;
+    case SPI_FLASH_QOUT:
+        ctrl.fread_quad = 1;
+        break;
+    case SPI_FLASH_DIO:
+        ctrl.fread_dio = 1;
+        break;
+    case SPI_FLASH_DOUT:
+        ctrl.fread_dual = 1;
+        break;
+    case SPI_FLASH_SLOWRD:
+        ctrl.fastrd_mode = 0;
+        break;
+    default:
+        abort();
+    }
+    dev->ctrl = ctrl;
+}
+
+/**
+ * Set clock frequency to work at.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param clock_val pointer to the clock value to set
+ */
+static inline void spimem_flash_ll_set_clock(spi_mem_dev_t *dev, spimem_flash_ll_clock_reg_t *clock_val)
+{
+    dev->clock.val = *clock_val;
+}
+
+/**
+ * Set the input length, in bits.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of input, in bits.
+ */
+static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
+{
+    dev->user.usr_miso = bitlen > 0;
+    dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0;
+}
+
+/**
+ * Set the output length, in bits (not including command, address and dummy
+ * phases)
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of output, in bits.
+ */
+static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
+{
+    dev->user.usr_mosi = bitlen > 0;
+    dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0;
+}
+
+/**
+ * Set the command.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param command Command to send
+ * @param bitlen Length of the command
+ */
+static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen)
+{
+    dev->user.usr_command = 1;
+    typeof(dev->user2) user2 = {
+        .usr_command_value = command,
+        .usr_command_bitlen = (bitlen - 1),
+    };
+    dev->user2 = user2;
+}
+
+/**
+ * Get the address length that is set in register, in bits.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ *
+ */
+static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
+{
+    return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
+}
+
+/**
+ * Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param bitlen Length of the address, in bits
+ */
+static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
+{
+    dev->user1.usr_addr_bitlen = (bitlen - 1);
+    dev->user.usr_addr = bitlen ? 1 : 0;
+}
+
+/**
+ * Set extra address for bits M0-M7 in DIO/QIO mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param extra_addr extra address(M0-M7) to send.
+ */
+static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
+{
+    dev->cache_fctrl.usr_addr_4byte = 0;
+    dev->rd_status.wb_mode = extra_addr;
+}
+
+/**
+ * Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param addr Address to send
+ */
+static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr)
+{
+    dev->addr = addr;
+}
+
+/**
+ * Set the address to send in user mode. Should be called before commands that requires the address e.g. erase sector, read, write...
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param addr Address to send
+ */
+static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
+{
+    (void)bitlen;
+    spimem_flash_ll_set_address(dev, addr);
+}
+
+/**
+ * Set the length of dummy cycles.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param dummy_n Cycles of dummy phases
+ */
+static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
+{
+    dev->user.usr_dummy = dummy_n ? 1 : 0;
+    dev->user1.usr_dummy_cyclelen = dummy_n - 1;
+}
+
+/**
+ * Set CS hold time.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param hold_n CS hold time config used by the host.
+ */
+static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
+{
+    dev->ctrl2.cs_hold_time = hold_n - 1;
+    dev->user.cs_hold = (hold_n > 0? 1: 0);
+}
+
+static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
+{
+    dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    dev->ctrl2.cs_setup_time = cs_setup_time - 1;
+}
+
+/**
+ * Get the spi flash source clock frequency. Used for calculating
+ * the divider parameters.
+ *
+ * @param None
+ *
+ * @return the frequency of spi flash clock source.(MHz)
+ */
+static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
+{
+// ESP32H2-TODO
+#if 0
+    // TODO: Default is PLL480M, this is hard-coded.
+    // In the future, we can get the CPU clock source by calling interface.
+    uint8_t clock_val = 0;
+    switch (SPIMEM0.core_clk_sel.spi01_clk_sel) {
+    case 0:
+        clock_val = 80;
+        break;
+    case 1:
+        clock_val = 120;
+        break;
+    case 2:
+        clock_val = 160;
+        break;
+    default:
+        abort();
+    }
+    return clock_val;
+#endif
+    return 80;
+}
+
+/**
+ * Calculate spi_flash clock frequency division parameters for register.
+ *
+ * @param clkdiv frequency division factor
+ *
+ * @return Register setting for the given clock division factor.
+ */
+static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
+{
+    uint32_t div_parameter;
+    // See comments of `clock` in `spi_mem_struct.h`
+    if (clkdiv == 1) {
+        div_parameter = (1 << 31);
+    } else {
+        div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
+    }
+    return div_parameter;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/systimer_ll.h

@@ -0,0 +1,159 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/systimer_struct.h"
+#include "hal/assert.h"
+
+#define SYSTIMER_LL_COUNTER_CLOCK       (0) // Counter used for "wallclock" time
+#define SYSTIMER_LL_COUNTER_OS_TICK     (1) // Counter used for OS tick
+#define SYSTIMER_LL_ALARM_OS_TICK_CORE0 (0) // Alarm used for OS tick of CPU core 0
+#define SYSTIMER_LL_ALARM_CLOCK         (2) // Alarm used for "wallclock" time
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// All these functions get invoked either from ISR or HAL that linked to IRAM.
+// Always inline these functions even no gcc optimization is applied.
+
+/******************* Clock *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
+{
+    dev->conf.clk_en = en;
+}
+
+/******************* Counter *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en)
+{
+    if (en) {
+        dev->conf.val |= 1 << (30 - counter_id);
+    } else {
+        dev->conf.val &= ~(1 << (30 - counter_id));
+    }
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can)
+{
+    if (can) {
+        dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id);
+    } else {
+        dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id));
+    }
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id)
+{
+    dev->unit_op[counter_id].timer_unit_update = 1;
+}
+
+__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_op[counter_id].timer_unit_value_valid;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value)
+{
+    dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32;
+    dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_val[counter_id].lo.timer_unit_value_lo;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_val[counter_id].hi.timer_unit_value_hi;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id)
+{
+    dev->unit_load[counter_id].val = 0x01;
+}
+
+/******************* Alarm *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value)
+{
+    dev->target_val[alarm_id].hi.timer_target_hi = value >> 32;
+    dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF;
+}
+
+__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
+{
+    dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->target_conf[alarm_id].target_period_mode = 0;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->target_conf[alarm_id].target_period_mode = 1;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
+{
+    HAL_ASSERT(period < (1 << 26));
+    dev->target_conf[alarm_id].target_period = period;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return dev->target_conf[alarm_id].target_period;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->comp_load[alarm_id].val = 0x01;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
+{
+    if (en) {
+        dev->conf.val |= 1 << (24 - alarm_id);
+    } else {
+        dev->conf.val &= ~(1 << (24 - alarm_id));
+    }
+}
+
+/******************* Interrupt *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en)
+{
+    if (en) {
+        dev->int_ena.val |= 1 << alarm_id;
+    } else {
+        dev->int_ena.val &= ~(1 << alarm_id);
+    }
+}
+
+__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return dev->int_st.val & (1 << alarm_id);
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->int_clr.val |= 1 << alarm_id;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h

@@ -0,0 +1,164 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer of the USB-serial-jtag controller
+
+#pragma once
+#include "soc/usb_serial_jtag_reg.h"
+#include "soc/usb_serial_jtag_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//The in and out endpoints are this long.
+#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64
+
+#define USB_SERIAL_JTAG_LL_INTR_MASK         (0x7ffff) //All interrupt mask
+
+// Define USB_SERIAL_JTAG interrupts
+// Note the hardware has more interrupts, but they're only useful for debugging
+// the hardware.
+typedef enum {
+    USB_SERIAL_JTAG_INTR_SOF                    = (1 << 1),
+    USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT    = (1 << 2),
+    USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY        = (1 << 3),
+    USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1       = (1 << 8),
+    USB_SERIAL_JTAG_INTR_BUS_RESET              = (1 << 9),
+    USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD       = (1 << 10),
+} usb_serial_jtag_ll_intr_t;
+
+/**
+ * @brief  Enable the USB_SERIAL_JTAG interrupt based on the given mask.
+ *
+ * @param  mask The bitmap of the interrupts need to be enabled.
+ *
+ * @return None
+ */
+static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask)
+{
+    USB_SERIAL_JTAG.int_ena.val |= mask;
+}
+
+/**
+ * @brief  Disable the USB_SERIAL_JTAG interrupt based on the given mask.
+ *
+ * @param  mask The bitmap of the interrupts need to be disabled.
+ *
+ * @return None
+ */
+static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask)
+{
+    USB_SERIAL_JTAG.int_ena.val &= (~mask);
+}
+
+/**
+ * @brief  Get the USB_SERIAL_JTAG interrupt status.
+ *
+ * @return The USB_SERIAL_JTAG interrupt status.
+ */
+static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void)
+{
+    return USB_SERIAL_JTAG.int_st.val;
+}
+
+/**
+ * @brief  Clear the USB_SERIAL_JTAG interrupt status based on the given mask.
+ *
+ * @param  mask The bitmap of the interrupts need to be cleared.
+ *
+ * @return None
+ */
+static inline void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask)
+{
+    USB_SERIAL_JTAG.int_clr.val = mask;
+}
+
+/**
+ * @brief  Get status of enabled interrupt.
+ *
+ * @return interrupt enable value
+ */
+static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void)
+{
+    return USB_SERIAL_JTAG.int_ena.val;
+}
+
+/**
+ * @brief  Read the bytes from the USB_SERIAL_JTAG rxfifo.
+ *
+ * @param  buf The data buffer.
+ * @param  rd_len The data length needs to be read.
+ *
+ * @return amount of bytes read
+ */
+static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
+{
+    int i;
+    for (i = 0; i < (int)rd_len; i++) {
+        if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
+        buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
+    }
+    return i;
+}
+
+/**
+ * @brief  Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there
+ *         is room in the buffer.
+ *
+ * @param  buf The data buffer.
+ * @param  wr_len The data length needs to be writen.
+ *
+ * @return Amount of bytes actually written. May be less than wr_len.
+ */
+static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len)
+{
+    int i;
+    for (i = 0; i < (int)wr_len; i++) {
+        if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
+        USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
+    }
+    return i;
+}
+
+/**
+ * @brief  Returns 1 if the USB_SERIAL_JTAG rxfifo has data available.
+ *
+ * @return 0 if no data available, 1 if data available
+ */
+static inline int usb_serial_jtag_ll_rxfifo_data_available(void)
+{
+    return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail;
+}
+
+/**
+ * @brief  Returns 1 if the USB_SERIAL_JTAG txfifo has room.
+ *
+ * @return 0 if no data available, 1 if data available
+ */
+static inline int usb_serial_jtag_ll_txfifo_writable(void)
+{
+    return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free;
+}
+
+/**
+ * @brief  Flushes the TX buffer, that is, make it available for the
+ *         host to pick up.
+ *
+ * @note  When fifo is full (with 64 byte), HW will flush the buffer automatically.
+ *        It won't be executed if there is nothing in the fifo.
+ *
+ * @return na
+ */
+static inline void usb_serial_jtag_ll_txfifo_flush(void)
+{
+    USB_SERIAL_JTAG.ep1_conf.wr_done=1;
+}
+
+
+#ifdef __cplusplus
+}
+#endif

components/hal/include/hal/gpio_types.h

@@ -385,6 +385,40 @@ typedef enum {
     GPIO_NUM_MAX,
 /** @endcond */
 } gpio_num_t;
+#elif CONFIG_IDF_TARGET_ESP32H2
+typedef enum {
+    GPIO_NUM_NC = -1,    /*!< Use to signal not connected to S/W */
+    GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
+    GPIO_NUM_1 = 1,     /*!< GPIO1, input and output */
+    GPIO_NUM_2 = 2,     /*!< GPIO2, input and output */
+    GPIO_NUM_3 = 3,     /*!< GPIO3, input and output */
+    GPIO_NUM_4 = 4,     /*!< GPIO4, input and output */
+    GPIO_NUM_5 = 5,     /*!< GPIO5, input and output */
+    GPIO_NUM_6 = 6,     /*!< GPIO6, input and output */
+    GPIO_NUM_7 = 7,     /*!< GPIO7, input and output */
+    GPIO_NUM_8 = 8,     /*!< GPIO8, input and output */
+    GPIO_NUM_9 = 9,     /*!< GPIO9, input and output */
+    GPIO_NUM_10 = 10,   /*!< GPIO10, input and output */
+    GPIO_NUM_11 = 11,   /*!< GPIO11, input and output */
+    GPIO_NUM_12 = 12,   /*!< GPIO12, input and output */
+    GPIO_NUM_13 = 13,   /*!< GPIO13, input and output */
+    GPIO_NUM_14 = 14,   /*!< GPIO14, input and output */
+    GPIO_NUM_15 = 15,   /*!< GPIO15, input and output */
+    GPIO_NUM_16 = 16,   /*!< GPIO16, input and output */
+    GPIO_NUM_17 = 17,   /*!< GPIO17, input and output */
+    GPIO_NUM_18 = 18,   /*!< GPIO18, input and output */
+    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
+    GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
+    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
+    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
+    GPIO_NUM_23 = 23,   /*!< GPIO23, input and output */
+    GPIO_NUM_24 = 24,   /*!< GPIO24, input and output */
+    GPIO_NUM_25 = 25,   /*!< GPIO25, input and output */
+    GPIO_NUM_26 = 26,   /*!< GPIO26, input and output */
+    GPIO_NUM_27 = 27,   /*!< GPIO27, input and output */
+    GPIO_NUM_MAX,
+/** @endcond */
+} gpio_num_t;
 #endif
 
 typedef enum {

components/hal/include/hal/sha_types.h

@@ -23,6 +23,8 @@
 #include "esp32c2/rom/sha.h"
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/sha.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/sha.h"
 #endif
 
 #ifdef __cplusplus

components/hal/include/hal/wdt_hal.h

@@ -29,7 +29,7 @@ typedef struct {
     wdt_inst_t inst;                /**< Which WDT instance this HAL context is using (i.e. MWDT0, MWDT1, RWDT)*/
     union {
         timg_dev_t *mwdt_dev;       /**< Starting address of the MWDT */
-#if CONFIG_IDF_TARGET_ESP32C6       // TODO: IDF-5653
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-5653
         lp_wdt_dev_t *rwdt_dev;     /**< Starting address of the RWDT*/
 #else
         rtc_cntl_dev_t *rwdt_dev;   /**< Starting address of the RWDT*/

components/hal/wdt_hal_iram.c

@@ -24,7 +24,7 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
     }
 #endif
     else {
-#if CONFIG_IDF_TARGET_ESP32C6       // TODO: IDF-5653
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2      // ESP32C6-TODO, ESP32H2-TODO: IDF-5653
         hal->rwdt_dev = &LP_WDT;
 #else
         hal->rwdt_dev = &RTCCNTL;

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -3,26 +3,6 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
-config SOC_DEDICATED_GPIO_SUPPORTED
-    bool
-    default y
-
-config SOC_GDMA_SUPPORTED
-    bool
-    default y
-
-config SOC_BT_SUPPORTED
-    bool
-    default y
-
-config SOC_ASYNC_MEMCPY_SUPPORTED
-    bool
-    default y
-
-config SOC_SUPPORTS_SECURE_DL_MODE
-    bool
-    default y
-
 config SOC_EFUSE_KEY_PURPOSE_FIELD
     bool
     default y
@@ -43,22 +23,6 @@ config SOC_SYSTIMER_SUPPORTED
     bool
     default y
 
-config SOC_SUPPORT_COEXISTENCE
-    bool
-    default y
-
-config SOC_MPI_SUPPORTED
-    bool
-    default y
-
-config SOC_HMAC_SUPPORTED
-    bool
-    default y
-
-config SOC_SECURE_BOOT_SUPPORTED
-    bool
-    default y
-
 config SOC_XTAL_SUPPORT_32M
     bool
     default y

components/soc/esp32h2/include/soc/pcr_struct.h

@@ -1791,12 +1791,12 @@ typedef union {
          *  This field indicates which one 32KHz clock will be used by timergroup. 0:
          *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
          */
-        uint32_t 32k_sel:2;
+        uint32_t clk_32k_sel:2;
         /** 32k_modem_sel : R/W; bitpos: [3:2]; default: 0;
          *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0:
          *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
          */
-        uint32_t 32k_modem_sel:2;
+        uint32_t clk_32k_modem_sel:2;
         uint32_t reserved_4:28;
     };
     uint32_t val;

components/soc/esp32h2/include/soc/soc_caps.h

@@ -26,16 +26,16 @@
 
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 // #define SOC_ADC_SUPPORTED               1 // TODO: IDF-6214
-#define SOC_DEDICATED_GPIO_SUPPORTED    1 // TODO: IDF-6241
+// #define SOC_DEDICATED_GPIO_SUPPORTED    1 // TODO: IDF-6241
-#define SOC_GDMA_SUPPORTED              1 // TODO: IDF-6222
+// #define SOC_GDMA_SUPPORTED              1 // TODO: IDF-6222
 // #define SOC_PCNT_SUPPORTED              1 // TODO: IDF-6221
 // #define SOC_MCPWM_SUPPORTED             1 // TODO: IDF-6237
 // #define SOC_TWAI_SUPPORTED              1 // TODO: IDF-6217
-#define SOC_BT_SUPPORTED                1
+// #define SOC_BT_SUPPORTED                1 // TODO: IDF-6416
-#define SOC_ASYNC_MEMCPY_SUPPORTED      1
+// #define SOC_ASYNC_MEMCPY_SUPPORTED      1 // TODO: IDF-6238
 // #define SOC_USB_SERIAL_JTAG_SUPPORTED   1 // TODO: IDF-6239
 // #define SOC_TEMP_SENSOR_SUPPORTED       1 // TODO: IDF-6229
-#define SOC_SUPPORTS_SECURE_DL_MODE     1
+// #define SOC_SUPPORTS_SECURE_DL_MODE     1 // TODO: IDF-6281
 //#define SOC_RISCV_COPROC_SUPPORTED       1 // TODO: IDF-6272
 #define SOC_EFUSE_KEY_PURPOSE_FIELD     1
 #define SOC_EFUSE_HAS_EFUSE_RST_BUG     1
@@ -45,14 +45,14 @@
 // #define SOC_RMT_SUPPORTED               1 // TODO: IDF-6224
 // #define SOC_SDM_SUPPORTED               1 // TODO: IDF-6220
 #define SOC_SYSTIMER_SUPPORTED          1
-#define SOC_SUPPORT_COEXISTENCE         1
+// #define SOC_SUPPORT_COEXISTENCE         1 // TODO: IDF-6416
 // #define SOC_AES_SUPPORTED               1 // TODO: IDF-6280
-#define SOC_MPI_SUPPORTED               1
+// #define SOC_MPI_SUPPORTED               1 // TODO: IDF-6415
 // #define SOC_SHA_SUPPORTED               1 // TODO: IDF-6275
-#define SOC_HMAC_SUPPORTED              1 // TODO: IDF-6279
+// #define SOC_HMAC_SUPPORTED              1 // TODO: IDF-6279
 // #define SOC_DIG_SIGN_SUPPORTED          1 // TODO: IDF-6285
 // #define SOC_FLASH_ENC_SUPPORTED         1 // TODO: IDF-6282
-#define SOC_SECURE_BOOT_SUPPORTED       1
+// #define SOC_SECURE_BOOT_SUPPORTED       1 // TODO: IDF-6281
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_32M            1