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https://github.com/espressif/esp-idf.git
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esp32: exclude DPORT-related code in single core mode
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@@ -41,6 +41,7 @@
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#include "xtensa/core-macros.h"
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#ifndef CONFIG_FREERTOS_UNICORE
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static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;
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#define DPORT_CORE_STATE_IDLE 0
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@@ -61,9 +62,9 @@ static uint32_t ccount_margin[portNUM_PROCESSORS][DPORT_ACCESS_BENCHMARK_STORE_N
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static uint32_t ccount_margin_cnt;
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#endif
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#ifndef CONFIG_FREERTOS_UNICORE
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static BaseType_t oldInterruptLevel[2];
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#endif
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#endif // CONFIG_FREERTOS_UNICORE
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/* stall other cpu that this cpu is pending to access dport register start */
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void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
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@@ -153,17 +154,17 @@ void IRAM_ATTR esp_dport_access_stall_other_cpu_end_wrap(void)
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DPORT_STALL_OTHER_CPU_END();
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}
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#ifndef CONFIG_FREERTOS_UNICORE
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static void dport_access_init_core(void *arg)
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{
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int core_id = 0;
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uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE;
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#ifndef CONFIG_FREERTOS_UNICORE
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core_id = xPortGetCoreID();
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if (core_id == 1) {
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intr_source = ETS_FROM_CPU_INTR3_SOURCE;
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}
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#endif
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ESP_INTR_DISABLE(ETS_DPORT_INUM);
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intr_matrix_set(core_id, intr_source, ETS_DPORT_INUM);
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@@ -176,40 +177,43 @@ static void dport_access_init_core(void *arg)
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vTaskDelete(NULL);
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}
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#endif
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/* Defer initialisation until after scheduler is running */
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void esp_dport_access_int_init(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portBASE_TYPE res = xTaskCreatePinnedToCore(&dport_access_init_core, "dport", configMINIMAL_STACK_SIZE, NULL, 5, NULL, xPortGetCoreID());
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assert(res == pdTRUE);
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_pause(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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#ifndef CONFIG_FREERTOS_UNICORE
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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#endif
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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//Used in panic code: the enter_critical stuff may be messed up so we just stop everything without checking the mux.
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void IRAM_ATTR esp_dport_access_int_abort(void)
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{
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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#ifndef CONFIG_FREERTOS_UNICORE
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dport_core_state[0] = DPORT_CORE_STATE_IDLE;
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dport_core_state[1] = DPORT_CORE_STATE_IDLE;
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#endif
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}
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void IRAM_ATTR esp_dport_access_int_resume(void)
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{
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#ifndef CONFIG_FREERTOS_UNICORE
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portENTER_CRITICAL_ISR(&g_dport_mux);
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dport_core_state[0] = DPORT_CORE_STATE_RUNNING;
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#ifndef CONFIG_FREERTOS_UNICORE
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dport_core_state[1] = DPORT_CORE_STATE_RUNNING;
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#endif
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portEXIT_CRITICAL_ISR(&g_dport_mux);
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#endif
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}
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