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Merge branch 'fix/crypto_periphs_use_rcc_atomic_blocks' into 'master'

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Use rcc atomic blocks to enable/reset crypto peripherals

See merge request espressif/esp-idf!25811
This commit is contained in:
Mahavir Jain
2023-10-13 22:37:58 +08:00
parent d73bf72885 57d10477da
commit 6b62065b92
34 changed files with 821 additions and 63 deletions
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32
components/hal/test_apps/crypto/main/ds/test_ds.c
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@@ -7,6 +7,7 @@
#include <string.h>
#include <assert.h>
#include "esp_private/esp_crypto_lock_internal.h"
#include "memory_checks.h"
#include "unity_fixture.h"
@@ -127,22 +128,39 @@ _Static_assert(NUM_RESULTS == NUM_MESSAGES, "expected_results size should be the
#include "hal/ds_hal.h"
#include "hal/ds_ll.h"
#include "hal/hmac_hal.h"
#include "hal/hmac_ll.h"
static void ds_acquire_enable(void)
{
periph_module_enable(PERIPH_HMAC_MODULE);
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(true);
hmac_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
periph_module_enable(PERIPH_DS_MODULE);
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(true);
ds_ll_reset_register();
}
hmac_hal_start();
}
static void ds_disable_release(void)
{
ds_hal_finish();
periph_module_disable(PERIPH_DS_MODULE);
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(false);
}
periph_module_disable(PERIPH_SHA_MODULE);
periph_module_disable(PERIPH_HMAC_MODULE);
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(false);
}
}
@@ -222,10 +240,7 @@ static esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
esp_err_t result = ESP_OK;
periph_module_enable(PERIPH_AES_MODULE);
periph_module_enable(PERIPH_DS_MODULE);
periph_module_enable(PERIPH_SHA_MODULE);
periph_module_enable(PERIPH_HMAC_MODULE);
periph_module_enable(PERIPH_RSA_MODULE);
ets_ds_data_t *ds_data = (ets_ds_data_t *) data;
const ets_ds_p_data_t *ds_plain_data = (const ets_ds_p_data_t *) p_data;
@@ -236,10 +251,7 @@ static esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
result = ESP_ERR_INVALID_ARG;
}
periph_module_disable(PERIPH_RSA_MODULE);
periph_module_disable(PERIPH_HMAC_MODULE);
periph_module_disable(PERIPH_SHA_MODULE);
periph_module_disable(PERIPH_DS_MODULE);
periph_module_disable(PERIPH_AES_MODULE);
return result;

30
components/hal/test_apps/crypto/main/ecc/test_ecc.c
View File

@@ -8,11 +8,12 @@
#include <stdbool.h>
#include <string.h>
#include "sdkconfig.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "esp_log.h"
#include "ecc_params.h"
#include "soc/soc_caps.h"
#include "hal/ecc_hal.h"
#include "hal/clk_gate_ll.h"
#include "hal/ecc_ll.h"
#include "memory_checks.h"
#include "unity_fixture.h"
@@ -43,7 +44,17 @@ static void ecc_be_to_le(const uint8_t* be_point, uint8_t *le_point, uint8_t len
static void ecc_enable_and_reset(void)
{
periph_ll_enable_clk_clear_rst(PERIPH_ECC_MODULE);
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(true);
ecc_ll_reset_register();
}
}
static void ecc_disable(void)
{
ECC_RCC_ATOMIC() {
ecc_ll_enable_bus_clock(false);
}
}
@@ -80,6 +91,7 @@ static void ecc_point_mul(const uint8_t *k_le, const uint8_t *x_le, const uint8_
}
ecc_hal_read_mul_result(res_x_le, res_y_le, len);
ecc_disable();
}
static void test_ecc_point_mul_inner(bool verify_first)
@@ -161,7 +173,10 @@ static int ecc_point_verify(const uint8_t *x_le, const uint8_t *y_le, uint8_t le
;
}
return ecc_hal_read_verify_result();
int ret = ecc_hal_read_verify_result();
ecc_disable();
return ret;
}
TEST(ecc, ecc_point_verification_on_SECP192R1_and_SECP256R1)
@@ -222,6 +237,7 @@ static void ecc_point_inv_mul(const uint8_t *num_le, const uint8_t *deno_le, uin
}
ecc_hal_read_mul_result(zero, res_le, len);
ecc_disable();
}
TEST(ecc, ecc_inverse_multiplication_or_mod_division_using_SECP192R1_and_SECP256R1_order_of_curve)
@@ -254,6 +270,7 @@ static void ecc_jacob_mul(uint8_t *k_le, uint8_t *x_le, uint8_t *y_le, uint8_t l
}
ecc_hal_read_jacob_mul_result(res_x_le, res_y_le, res_z_le, len);
ecc_disable();
}
static void test_ecc_jacob_mul_inner(bool verify_first)
@@ -314,7 +331,10 @@ static int ecc_jacob_verify(const uint8_t *x_le, const uint8_t *y_le, const uint
;
}
return ecc_hal_read_verify_result();
int ret = ecc_hal_read_verify_result();
ecc_disable();
return ret;
}
TEST(ecc, ecc_jacobian_point_verification_on_SECP192R1_and_SECP256R1)
@@ -355,6 +375,7 @@ static void ecc_point_addition(uint8_t *px_le, uint8_t *py_le, uint8_t *qx_le, u
}
ecc_hal_read_point_add_result(x_res_le, y_res_le, z_res_le, len, jacob_output);
ecc_disable();
}
TEST(ecc, ecc_point_addition_on_SECP192R1_and_SECP256R1)
@@ -426,6 +447,7 @@ static void ecc_mod_op(ecc_mode_t mode, const uint8_t *a, const uint8_t *b, uint
}
ecc_hal_read_mod_op_result(res_le, len);
ecc_disable();
}
#endif

21
components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c
View File

@@ -8,10 +8,11 @@
#include <stdbool.h>
#include <string.h>
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "esp_random.h"
#include "hal/clk_gate_ll.h"
#include "hal/ecdsa_hal.h"
#include "hal/ecdsa_ll.h"
#include "hal/ecdsa_types.h"
#include "memory_checks.h"
@@ -19,15 +20,19 @@
#include "ecdsa_params.h"
static void ecdsa_enable_and_reset(void)
{
periph_ll_enable_clk_clear_rst(PERIPH_ECDSA_MODULE);
ECDSA_RCC_ATOMIC() {
ecdsa_ll_enable_bus_clock(true);
ecdsa_ll_reset_register();
}
}
static void ecdsa_disable_and_reset(void)
static void ecdsa_disable(void)
{
periph_ll_disable_clk_set_rst(PERIPH_ECDSA_MODULE);
ECDSA_RCC_ATOMIC() {
ecdsa_ll_enable_bus_clock(false);
}
}
static void ecc_be_to_le(const uint8_t* be_point, uint8_t *le_point, uint8_t len)
@@ -62,7 +67,7 @@ static int test_ecdsa_verify(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t*
ecdsa_enable_and_reset();
int ret = ecdsa_hal_verify_signature(&conf, sha_le, r_le, s_le, pub_x, pub_y, len);
ecdsa_disable_and_reset();
ecdsa_disable();
return ret;
}
@@ -142,7 +147,7 @@ static void test_ecdsa_sign(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t*
ecdsa_hal_gen_signature(&conf, NULL, sha_le, r_le, s_le, len);
} while(!memcmp(r_le, zeroes, len) || !memcmp(s_le, zeroes, len));
ecdsa_disable_and_reset();
ecdsa_disable();
}
static void test_ecdsa_sign_and_verify(bool is_p256, uint8_t* sha, uint8_t* pub_x, uint8_t* pub_y, bool use_km_key)
@@ -191,7 +196,7 @@ static void test_ecdsa_export_pubkey(bool is_p256, bool use_km_key)
TEST_ASSERT_EQUAL_HEX8_ARRAY(ecdsa192_pub_y, pub_y, len);
}
ecdsa_disable_and_reset();
ecdsa_disable();
}
#endif /* SOC_ECDSA_SUPPORT_EXPORT_PUBKEY */

25
components/hal/test_apps/crypto/main/hmac/test_hmac.c
View File

@@ -5,6 +5,7 @@
*/
#include <string.h>
#include "esp_private/esp_crypto_lock_internal.h"
#include "esp_log.h"
#include "memory_checks.h"
#include "unity_fixture.h"
@@ -39,6 +40,8 @@ static esp_err_t hmac_jtag_disable(void)
#if !CONFIG_IDF_TARGET_ESP32S2
#include "hal/hmac_hal.h"
#include "hal/hmac_ll.h"
#include "hal/ds_ll.h"
#include "esp_private/periph_ctrl.h"
#define SHA256_BLOCK_SZ 64
@@ -70,9 +73,17 @@ static esp_err_t hmac_calculate(hmac_key_id_t key_id, const void *message, size_
{
const uint8_t *message_bytes = (const uint8_t *)message;
periph_module_enable(PERIPH_HMAC_MODULE);
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(true);
hmac_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
periph_module_enable(PERIPH_DS_MODULE);
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(true);
ds_ll_reset_register();
}
hmac_hal_start();
@@ -124,9 +135,15 @@ static esp_err_t hmac_calculate(hmac_key_id_t key_id, const void *message, size_
hmac_hal_read_result_256(hmac);
periph_module_disable(PERIPH_DS_MODULE);
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(false);
}
periph_module_disable(PERIPH_SHA_MODULE);
periph_module_disable(PERIPH_HMAC_MODULE);
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(false);
}
return ESP_OK;
}

13
components/hal/test_apps/crypto/main/mpi/test_mpi.c
View File

@@ -6,8 +6,8 @@
#include <stdio.h>
#include <string.h>
#include "esp_private/esp_crypto_lock_internal.h"
#include "esp_log.h"
#include "esp_private/periph_ctrl.h"
#include "esp_heap_caps.h"
#include "memory_checks.h"
#include "unity_fixture.h"
@@ -17,15 +17,18 @@
#endif
#include "hal/mpi_hal.h"
#include "hal/mpi_ll.h"
#include "mpi_params.h"
#define _DEBUG_ 0
static void esp_mpi_enable_hardware_hw_op( void )
{
/* Enable RSA hardware */
periph_module_enable(PERIPH_RSA_MODULE);
MPI_RCC_ATOMIC() {
mpi_ll_enable_bus_clock(true);
mpi_ll_reset_register();
}
mpi_hal_enable_hardware_hw_op();
}
@@ -36,7 +39,9 @@ static void esp_mpi_disable_hardware_hw_op( void )
mpi_hal_disable_hardware_hw_op();
/* Disable RSA hardware */
periph_module_disable(PERIPH_RSA_MODULE);
MPI_RCC_ATOMIC() {
mpi_ll_enable_bus_clock(false);
}
}