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feat(rmt): add driver support for esp32p4

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including DMA feature
This commit is contained in:
morris
2023-08-01 17:32:26 +08:00
parent 80e3ece7d1
commit 6bb05cccdd
42 changed files with 1882 additions and 593 deletions
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20
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -55,6 +55,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_RMT_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
@@ -489,15 +493,15 @@ config SOC_RMT_GROUPS
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 2
default 4
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 2
default 4
config SOC_RMT_CHANNELS_PER_GROUP
int
default 4
default 8
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
@@ -515,6 +519,14 @@ config SOC_RMT_SUPPORT_TX_ASYNC_STOP
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP
bool
default y
config SOC_RMT_SUPPORT_TX_SYNCHRO
bool
default y
@@ -527,7 +539,7 @@ config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_RMT_SUPPORT_RC_FAST
config SOC_RMT_SUPPORT_DMA
bool
default y

36
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -213,6 +213,42 @@ typedef enum {
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of RMT
*/
#if SOC_CLK_TREE_SUPPORTED
#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
#else
#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL}
#endif
/**
* @brief Type of RMT clock source
*/
typedef enum {
RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
#else
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
#endif
} soc_periph_rmt_clk_src_t;
/**
* @brief Type of RMT clock source, reserved for the legacy RMT driver
*/
typedef enum {
RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
#if SOC_CLK_TREE_SUPPORTED
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
#else
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */
#endif
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////

586
components/soc/esp32p4/include/soc/rmt_struct.h
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File diff suppressed because it is too large Load Diff

15
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -49,7 +49,7 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
// #define SOC_I2S_SUPPORTED 1 //TODO: IDF-6508
// #define SOC_RMT_SUPPORTED 1 //TODO: IDF-7476
#define SOC_RMT_SUPPORTED 1
// #define SOC_SDM_SUPPORTED 1 //TODO: IDF-7551
// #define SOC_GPSPI_SUPPORTED 1 //TODO: IDF-7502, TODO: IDF-7503
// #define SOC_LEDC_SUPPORTED 1 //TODO: IDF-6510
@@ -271,19 +271,20 @@
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS 1U /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP 4 /*!< Number of channels that capable of Transmit in each group */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP 4 /*!< Number of channels that capable of Receive in each group */
#define SOC_RMT_CHANNELS_PER_GROUP 8 /*!< Total 8 channels */
#define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
#define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
// #define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
// #define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */ //TODO: IDF-7476
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */
#define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
#define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST clock as the RMT clock source */
#define SOC_RMT_SUPPORT_DMA 1 /*!< RMT peripheral can connect to DMA channel */
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS (2U) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)

4
components/soc/esp32p4/ld/esp32p4.peripherals.ld
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@@ -17,8 +17,8 @@ PROVIDE ( SPIMEM3 = 0x5008F000 );
PROVIDE ( I2C0 = 0x500C4000 );
PROVIDE ( I2C1 = 0x500C5000 );
PROVIDE ( UHCI0 = 0x500DF000 );
PROVIDE ( RMT = 0x500D4000 );
PROVIDE ( RMTMEM = 0x500D4800 );
PROVIDE ( RMT = 0x500A2000 );
PROVIDE ( RMTMEM = 0x500A2800 );
PROVIDE ( LEDC = 0x500D3000 );
PROVIDE ( TIMERG0 = 0x500C2000 );
PROVIDE ( TIMERG1 = 0x500C3000 );

41
components/soc/esp32p4/rmt_periph.c
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@@ -8,5 +8,44 @@
#include "soc/gpio_sig_map.h"
const rmt_signal_conn_t rmt_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_RMT_MODULE,
.irq = ETS_RMT_INTR_SOURCE,
.channels = {
[0] = {
.tx_sig = RMT_SIG_PAD_OUT0_IDX,
.rx_sig = -1
},
[1] = {
.tx_sig = RMT_SIG_PAD_OUT1_IDX,
.rx_sig = -1
},
[2] = {
.tx_sig = RMT_SIG_PAD_OUT2_IDX,
.rx_sig = -1
},
[3] = {
.tx_sig = RMT_SIG_PAD_OUT3_IDX,
.rx_sig = -1
},
[4] = {
.tx_sig = -1,
.rx_sig = RMT_SIG_PAD_IN0_IDX
},
[5] = {
.tx_sig = -1,
.rx_sig = RMT_SIG_PAD_IN1_IDX
},
[6] = {
.tx_sig = -1,
.rx_sig = RMT_SIG_PAD_IN2_IDX
},
[7] = {
.tx_sig = -1,
.rx_sig = RMT_SIG_PAD_IN3_IDX
}
}
}
}
};