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fast_gpio: driver support on esp32c3

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This commit is contained in:
morris
2021-08-27 12:18:12 +08:00
parent bc3c9d27f6
commit 6cec256a34
14 changed files with 206 additions and 30 deletions
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41
components/soc/esp32c3/include/soc/gpio_sig_map.h
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@@ -53,26 +53,26 @@
#define GPIO_WLAN_PRIO_IDX 18
#define GPIO_BT_ACTIVE_IDX 19
#define GPIO_WLAN_ACTIVE_IDX 19
#define BB_DIAG0_IDX 20
#define BB_DIAG1_IDX 21
#define BB_DIAG2_IDX 22
#define BB_DIAG3_IDX 23
#define BB_DIAG4_IDX 24
#define BB_DIAG5_IDX 25
#define BB_DIAG6_IDX 26
#define BB_DIAG7_IDX 27
#define BB_DIAG8_IDX 28
#define BB_DIAG9_IDX 29
#define BB_DIAG10_IDX 30
#define BB_DIAG11_IDX 31
#define BB_DIAG12_IDX 32
#define BB_DIAG13_IDX 33
#define BB_DIAG14_IDX 34
#define BB_DIAG15_IDX 35
#define BB_DIAG16_IDX 36
#define BB_DIAG17_IDX 37
#define BB_DIAG18_IDX 38
#define BB_DIAG19_IDX 39
#define CPU_GPIO_IN0_IDX 28
#define CPU_GPIO_OUT0_IDX 28
#define CPU_GPIO_IN1_IDX 29
#define CPU_GPIO_OUT1_IDX 29
#define CPU_GPIO_IN2_IDX 30
#define CPU_GPIO_OUT2_IDX 30
#define CPU_GPIO_IN3_IDX 31
#define CPU_GPIO_OUT3_IDX 31
#define CPU_GPIO_IN4_IDX 32
#define CPU_GPIO_OUT4_IDX 32
#define CPU_GPIO_IN5_IDX 33
#define CPU_GPIO_OUT5_IDX 33
#define CPU_GPIO_IN6_IDX 34
#define CPU_GPIO_OUT6_IDX 34
#define CPU_GPIO_IN7_IDX 35
#define CPU_GPIO_OUT7_IDX 35
#define USB_JTAG_TCK_OUT_IDX 36
#define USB_JTAG_TMS_OUT_IDX 37
#define USB_JTAG_TDI_OUT_IDX 38
#define USB_JTAG_TDO_OUT_IDX 39
#define USB_EXTPHY_VP_IDX 40
#define USB_EXTPHY_OEN_IDX 40
#define USB_EXTPHY_VM_IDX 41
@@ -179,6 +179,7 @@
#define CLK_OUT_OUT2_IDX 124
#define CLK_OUT_OUT3_IDX 125
#define SPICS1_OUT_IDX 126
#define USB_JTAG_TRST_OUT_IDX 127
#define SIG_GPIO_OUT_IDX 128
#define GPIO_MAP_DATE_IDX 0x2006130
#endif /* _SOC_GPIO_SIG_MAP_H_ */

6
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -6,6 +6,7 @@
#pragma once
#define SOC_CPU_CORES_NUM 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
@@ -97,6 +98,11 @@
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_AUTO_ENABLE (1) /*!< The dedicated GPIO peripheral is enabled automatically */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 have 2 I2C.
#define SOC_I2C_NUM (1)