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efuse: Adds ERR_RST_ENABLE efuse for C3 and S3

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Closes https://github.com/espressif/esp-idf/issues/8357
This commit is contained in:
KonstantinKondrashov
2022-02-28 21:16:24 +08:00
parent 6e0308d352
commit 6d11c57b2a
11 changed files with 93 additions and 59 deletions
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42
components/soc/esp32c3/include/soc/efuse_reg.h
View File

@@ -256,11 +256,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved (used for four backups method).*/
#define EFUSE_RPT4_RESERVED1 0x00000003
#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
#define EFUSE_RPT4_RESERVED1_V 0x3
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: Secure version (used by ESP-IDF anti-rollback feature).*/
@@ -609,11 +615,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_S 0
#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C)
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE (BIT(31))
#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_V 0x1
#define EFUSE_ERR_RST_ENABLE_S 31
/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1 0x00000003
#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
#define EFUSE_RPT4_RESERVED1_V 0x3
#define EFUSE_RPT4_RESERVED1 (BIT(30))
#define EFUSE_RPT4_RESERVED1_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_V 0x1
#define EFUSE_RPT4_RESERVED1_S 30
/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: The value of SECURE_VERSION.*/
@@ -1561,11 +1573,17 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_2_ERR_S 0
#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */
/* EFUSE_ERR_RST_ENABLE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
#define EFUSE_ERR_RST_ENABLE_ERR (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_M (BIT(31))
#define EFUSE_ERR_RST_ENABLE_ERR_V 0x1
#define EFUSE_ERR_RST_ENABLE_ERR_S 31
/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED1_ERR 0x00000003
#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x3
#define EFUSE_RPT4_RESERVED1_ERR (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30))
#define EFUSE_RPT4_RESERVED1_ERR_V 0x1
#define EFUSE_RPT4_RESERVED1_ERR_S 30
/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/

9
components/soc/esp32c3/include/soc/efuse_struct.h
View File

@@ -75,7 +75,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7: 5; /*Reserved (used for four backups method).*/
uint32_t force_send_resume: 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
uint32_t secure_version: 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/
uint32_t rpt4_reserved1: 2; /*Reserved (used for four backups method).*/
uint32_t rpt4_reserved1: 1; /*Reserved (used for four backups method).*/
uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} pgm_data4;
@@ -156,7 +157,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7: 5; /*Reserved.*/
uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/
uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/
uint32_t rpt4_reserved1: 2; /*Reserved.*/
uint32_t rpt4_reserved1: 1; /*Reserved.*/
uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_data3;
@@ -323,7 +325,8 @@ typedef volatile struct efuse_dev_s {
uint32_t rpt4_reserved7_err: 5; /*Reserved*/
uint32_t force_send_resume_err: 1; /*If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/
uint32_t secure_version_err: 16; /*If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/
uint32_t rpt4_reserved1_err: 2; /*Reserved.*/
uint32_t rpt4_reserved1_err: 1; /*Reserved.*/
uint32_t err_rst_enable_err: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
};
uint32_t val;
} rd_repeat_err3;