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gpio: Add support for esp32c6

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This commit is contained in:
Song Ruo Jing
2022-09-27 15:18:40 +08:00
parent 439455b440
commit 6d24e8bcf4
24 changed files with 165 additions and 254 deletions
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6
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
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@@ -231,11 +231,7 @@ config SOC_GPIO_PIN_COUNT
int
default 31
config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_FORCE_HOLD
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y

9
components/soc/esp32c6/include/soc/clkout_channel.h
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@@ -7,13 +7,6 @@
#ifndef _SOC_CLKOUT_CHANNEL_H
#define _SOC_CLKOUT_CHANNEL_H
// TODO: IDF-5870
//CLKOUT channels
#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1
#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20
#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2
#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19
#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3
#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18
// ESP32C6 CLKOUT signals has no corresponding iomux pins
#endif

53
components/soc/esp32c6/include/soc/io_mux_reg.h
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@@ -13,7 +13,7 @@
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
/* Used to enable sleep mode pin functions */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
@@ -64,14 +64,25 @@
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
@@ -125,7 +136,10 @@
#define SD_DATA2_GPIO_NUM 22
#define SD_DATA3_GPIO_NUM 23
#define MAX_RTC_GPIO_NUM 5
#define USB_DM_GPIO_NUM 12
#define USB_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 8
#define MAX_PAD_GPIO_NUM 30
#define MAX_GPIO_NUM 34
#define DIG_IO_HOLD_BIT_SHIFT 32
@@ -133,25 +147,16 @@
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0xf
#define CLK_OUT3 0x1f
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
#define CLK_OUT3_S 10
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0xf
#define CLK_OUT2 0x1f
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 4
#define CLK_OUT2_S 5
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0xf
#define CLK_OUT1 0x1f
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)

20
components/soc/esp32c6/include/soc/soc_caps.h
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@@ -139,23 +139,20 @@
#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
// TODO: IDF-5321 (Copy from esp32c3, need check)
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C6 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT (31)
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-C6
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C6 can support chip deep sleep wakeup
// Target has the full LP IO subsystem
// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// GPIO0~7 on ESP32C6 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
@@ -163,6 +160,13 @@
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
// TODO: IDF-6027
// #define SOC_RTCIO_PIN_COUNT 8
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
// #define SOC_RTCIO_HOLD_SUPPORTED 1 (does not have force_hold_all feature, but has deep_sleep_hold_all feature)
// #define SOC_RTCIO_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */