feat(clk): Add basic clock support for esp32h21

components/soc/esp32c2/include/soc/clk_tree_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,6 +34,9 @@ extern "C" {
  *    OSC_SLOW_CLK can also be calibrated to get its exact frequency.
  */
 
+/* The pin number to connect the external slow clock (OSC_SLOW_CLK), XTAL_32K_P */
+#define SOC_EXT_OSC_SLOW_GPIO_NUM           0
+
 /* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
 #define SOC_CLK_RC_FAST_FREQ_APPROX         17500000                            /*!< Approximate RC_FAST_CLK frequency in Hz */
 #define SOC_CLK_RC_SLOW_FREQ_APPROX         136000                              /*!< Approximate RC_SLOW_CLK frequency in Hz */
@@ -54,6 +57,13 @@ typedef enum {
     SOC_ROOT_CLK_EXT_OSC_SLOW,         /*!< External slow clock signal at pin0, only support 32.768 KHz currently */
 } soc_root_clk_t;
 
+/**
+ * @brief ROOT clock circuit, which requires explicitly enabling the targeting circuit to use
+ */
+typedef enum {
+    SOC_ROOT_CIRCUIT_CLK_BBPLL,         /*!< BBPLL_CLK is the output of the BBPLL generator circuit */
+} soc_root_clk_circuit_t;
+
 /**
  * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
  * @note Enum values are matched with the register field values on purpose

components/soc/esp32c2/register/soc/io_mux_reg.h

@@ -129,8 +129,6 @@
 #define SPI_D_GPIO_NUM               16
 #define SPI_Q_GPIO_NUM               17
 
-#define EXT_OSC_SLOW_GPIO_NUM        0
-
 #define MAX_RTC_GPIO_NUM              5
 #define MAX_PAD_GPIO_NUM             20
 #define MAX_GPIO_NUM                 24