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feat(clk): Add basic clock support for esp32h21

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This commit is contained in:
Song Ruo Jing
2025-03-04 16:53:52 +08:00
parent 2fb938c7c3
commit 6d293c8582
90 changed files with 833 additions and 858 deletions
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12
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -51,6 +51,9 @@ extern "C" {
* 6) LP_PLL (8MHz), used for RTC_FAST_CLK clock source and LP peripherals' clock sources
*/
/* The pin number to connect the external slow clock (OSC_SLOW_CLK), XTAL_32K_N */
#define SOC_EXT_OSC_SLOW_GPIO_NUM 0
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
@@ -73,6 +76,15 @@ typedef enum {
SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin1 */
} soc_root_clk_t;
/**
* @brief ROOT clock circuit, which requires explicitly enabling the targeting circuit to use
*/
typedef enum {
SOC_ROOT_CIRCUIT_CLK_CPLL, /*!< CPLL_CLK is the output of the CPLL generator circuit */
SOC_ROOT_CIRCUIT_CLK_APLL, /*!< APLL_CLK is the output of the APLL generator circuit */
SOC_ROOT_CIRCUIT_CLK_MPLL, /*!< MPLL_CLK is the output of the MPLL generator circuit */
} soc_root_clk_circuit_t;
/**
* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
* @note Enum values are matched with the register field values on purpose