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feat(gdma): test non-cacheable DMA descriptor

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To avoid different DMA descriptors reside in the same cache line,
we want the CPU to access the DMA descriptor in a non-cachable way
This commit is contained in:
morris
2023-07-24 15:16:40 +08:00
parent 3b7da7eae5
commit 6d46cf739c
2 changed files with 52 additions and 24 deletions
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7
components/hal/esp32p4/include/hal/cache_ll.h
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@@ -17,6 +17,12 @@
extern "C" {
#endif
/**
* @brief Given a L2MEM cached address, get the corresponding non-cacheable address
* @example 0x4FF0_0000 => 0x8FF0_0000
*/
#define CACHE_LL_L2MEM_NON_CACHE_ADDR(addr) ((intptr_t)(addr) + 0x40000000)
#define CACHE_LL_ENABLE_DISABLE_STATE_SW 1 //There's no register indicating cache enable/disable state, we need to use software way for this state.
#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
@@ -36,7 +42,6 @@ extern "C" {
// #define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1)
// #define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0)
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*