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esp32c3: memprot API upgrade and test application
Closes IDF-2641
This commit is contained in:
Martin Vychodil
committed by
Angus Gratton
Angus Gratton
parent
2ed3e8b344
commit
6dfff2fdbd
@@ -0,0 +1,71 @@
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// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "riscv/rvruntime-frames.h"
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/* The riscv panic handler in components/riscv/vectors.S doesn't allow the panic
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handler function to return.
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However, for the purposes of this test we want to allow the panic handler to return.
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There is functionality in vectors.S restore the CPU state, but it only
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restores when CONTEXT_SIZE registers are
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pushed onto the stack not RV_STK_FRMSZ registers
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Instead of messing with that, implement a full "restore from RvExcFrame"
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function here which restores the CPU and then
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returns from exception.
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Called as return_from_panic_handler(RvExcFrame *frame)
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*/
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.global return_from_panic_handler
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return_from_panic_handler:
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or t0, a0, a0 /* use t0 as the working register */
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/* save general registers */
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lw ra, RV_STK_RA(t0)
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lw sp, RV_STK_SP(t0)
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lw gp, RV_STK_GP(t0)
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lw tp, RV_STK_TP(t0)
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lw s0, RV_STK_S0(t0)
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lw s1, RV_STK_S1(t0)
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lw a0, RV_STK_A0(t0)
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lw a1, RV_STK_A1(t0)
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lw a2, RV_STK_A2(t0)
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lw a3, RV_STK_A3(t0)
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lw a4, RV_STK_A4(t0)
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lw a5, RV_STK_A5(t0)
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lw a6, RV_STK_A6(t0)
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lw a7, RV_STK_A7(t0)
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lw s2, RV_STK_S2(t0)
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lw s3, RV_STK_S3(t0)
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lw s4, RV_STK_S4(t0)
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lw s5, RV_STK_S5(t0)
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lw s6, RV_STK_S6(t0)
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lw s7, RV_STK_S7(t0)
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lw s8, RV_STK_S8(t0)
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lw s9, RV_STK_S9(t0)
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lw s10, RV_STK_S10(t0)
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lw s11, RV_STK_S11(t0)
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lw t3, RV_STK_T3(t0)
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lw t4, RV_STK_T4(t0)
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lw t5, RV_STK_T5(t0)
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lw t6, RV_STK_T6(t0)
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lw t2, RV_STK_MEPC(t0)
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csrw mepc, t2
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lw t1, RV_STK_T1(t0)
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lw t2, RV_STK_T2(t0)
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lw t0, RV_STK_T0(t0)
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mret
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392
tools/test_apps/system/memprot/main/esp32c3/test_memprot_main.c
Normal file
392
tools/test_apps/system/memprot/main/esp32c3/test_memprot_main.c
Normal file
@@ -0,0 +1,392 @@
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/* MEMPROT (PMS) testing code */
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#include <stdio.h>
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#include "sdkconfig.h"
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#include "esp32c3/memprot.h"
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#include "esp_rom_sys.h"
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#include <string.h>
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/**
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* ESP32C3 MEMORY PROTECTION MODULE TEST
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* =====================================
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*
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* In order to safely test all the memprot features, this test application uses memprot default settings
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* plus proprietary testing buffers:
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* - iram_test_buffer (.iram_end_test, 1kB) - all low region operations
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* - dram_test_buffer (.dram0.data, 1kB) - all high region operations
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* Testing addresses are set to the middle of the testing buffers:
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* - test_ptr_low = iram_test_buffer + 0x200
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* - test_ptr_high = dram_test_buffer + 0x200
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* Each operation is tested at both low & high region addresses.
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* Each test result checked against expected status of PMS violation interrupt status and
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* against expected value stored in the memory tested (where applicable)
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*
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* Testing scheme is depicted below:
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*
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* DRam0/DMA IRam0
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* -----------------------------------------------
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* | IRam0_PMS_0 = IRam0_PMS_1 = IRam0_PMS_2 |
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* | DRam0_PMS_0 |
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* | |
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* | |
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* | - - - - - - - iram_test_buffer - - - - - - -| IRam0_line1_Split_addr
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* DRam0_DMA_line0_Split_addr | -- test_ptr_low -- | =
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* = =============================================== IRam0_line0_Split_addr
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* DRam0_DMA_line1_Split_addr | | =
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* | - - - - - - - dram_test_buffer - - - - - - -| IRam0_DRam0_Split_addr (main I/D)
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* | -- test_ptr_high -- |
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* | - - - - - - - - - - - - - - - - - - - - - - |
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* | |
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* | DRam0_PMS_1 = DRam0_PMS_2 = DRam0_PMS_3 |
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* | IRam0_PMS_3 |
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* -----------------------------------------------
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*
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* For more details on PMS memprot settings see 'esp_memprot_set_prot_int' function in esp32c3/memprot.h
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*/
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/* Binary code for the following asm [int func(int x) { return x+x; }]
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slli a0,a0,0x1
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ret
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*/
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static uint8_t fnc_buff[] = { 0x06, 0x05, 0x82, 0x80 };
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typedef int (*fnc_ptr)(int);
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#define SRAM_TEST_BUFFER_SIZE 0x400
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#define SRAM_TEST_OFFSET 0x200
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static uint8_t __attribute__((section(".iram_end_test"))) iram_test_buffer[SRAM_TEST_BUFFER_SIZE] = {0};
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static uint8_t dram_test_buffer[SRAM_TEST_BUFFER_SIZE] = {0};
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extern volatile bool g_override_illegal_instruction;
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static void *test_memprot_addr_low(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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return (void*)((uint32_t)iram_test_buffer + SRAM_TEST_OFFSET);
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case MEMPROT_DRAM0_SRAM:
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return (void*)MAP_IRAM_TO_DRAM((uint32_t)iram_test_buffer + SRAM_TEST_OFFSET);
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default:
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abort();
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}
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}
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static void *test_memprot_addr_high(mem_type_prot_t mem_type)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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return (void*)MAP_DRAM_TO_IRAM((uint32_t)dram_test_buffer + SRAM_TEST_OFFSET);
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case MEMPROT_DRAM0_SRAM:
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return (void*)((uint32_t)dram_test_buffer + SRAM_TEST_OFFSET);
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default:
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abort();
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}
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}
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static void __attribute__((unused)) dump_status_register(mem_type_prot_t mem_type)
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{
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char operation = 0;
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// IRAM fault: check instruction-fetch flag
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if ( mem_type == MEMPROT_IRAM0_SRAM ) {
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if ( esp_memprot_get_violate_loadstore(mem_type) ) {
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operation = 'X';
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}
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}
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// W/R - common
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if ( operation == 0 ) {
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operation = esp_memprot_get_violate_wr(mem_type) == MEMPROT_PMS_OP_WRITE ? 'W' : 'R';
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}
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esp_rom_printf(
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" FAULT [ world: %u, fault addr: 0x%08X, operation: %c",
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esp_memprot_get_violate_world(mem_type),
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esp_memprot_get_violate_addr(mem_type),
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operation
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);
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// DRAM/DMA fault: check byte-enables
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if ( mem_type == MEMPROT_DRAM0_SRAM ) {
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esp_rom_printf( ", byte en: 0x%08X", esp_memprot_get_violate_byte_en(mem_type) );
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}
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esp_rom_printf( " ]\n" );
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}
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static void check_test_result(mem_type_prot_t mem_type, bool expected_status)
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{
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bool test_result =
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expected_status ?
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!esp_memprot_get_violate_intr_on(mem_type) :
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esp_memprot_get_violate_intr_on(mem_type);
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if ( test_result ) {
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esp_rom_printf("OK\n");
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} else {
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dump_status_register(mem_type);
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}
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}
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static void test_memprot_get_permissions(bool low, mem_type_prot_t mem_type, bool *read, bool *write, bool *exec )
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{
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bool _r, _w, _x;
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pms_area_t area = MEMPROT_PMS_AREA_NONE;
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM:
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area = low ? MEMPROT_IRAM0_PMS_AREA_2 : MEMPROT_IRAM0_PMS_AREA_3;
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esp_memprot_iram_get_pms_area(area, &_r, &_w, &_x);
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break;
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case MEMPROT_DRAM0_SRAM:
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area = low ? MEMPROT_DRAM0_PMS_AREA_0 : MEMPROT_DRAM0_PMS_AREA_1;
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esp_memprot_dram_get_pms_area(area, &_r, &_w);
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break;
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default:
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abort();
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}
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if ( read ) {
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*read = _r;
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}
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if ( write ) {
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*write = _w;
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}
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if ( exec ) {
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*exec = _x;
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}
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}
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static void test_memprot_set_permissions(bool low, mem_type_prot_t mem_type, bool read, bool write, bool *exec)
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{
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switch ( mem_type ) {
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case MEMPROT_IRAM0_SRAM: {
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bool _ex;
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if (!exec) {
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test_memprot_get_permissions( low, mem_type, NULL, NULL, &_ex);
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exec = &_ex;
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}
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if (low) {
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_0, read, write, *exec);
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_1, read, write, *exec);
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_2, read, write, *exec);
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} else {
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esp_memprot_iram_set_pms_area(MEMPROT_IRAM0_PMS_AREA_3, read, write, *exec);
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}
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}
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break;
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case MEMPROT_DRAM0_SRAM: {
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if (low) {
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esp_memprot_dram_set_pms_area( MEMPROT_DRAM0_PMS_AREA_0, read, write );
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} else {
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_1, read, write);
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_2, read, write);
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esp_memprot_dram_set_pms_area(MEMPROT_DRAM0_PMS_AREA_3, read, write);
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}
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}
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break;
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default:
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abort();
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}
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}
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static void test_memprot_read(mem_type_prot_t mem_type)
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{
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//get current READ & WRITE permission settings
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bool write_perm_low, write_perm_high, read_perm_low, read_perm_high, exec_perm_low, exec_perm_high;
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test_memprot_get_permissions(true, mem_type, &read_perm_low, &write_perm_low, mem_type == MEMPROT_IRAM0_SRAM ? &exec_perm_low : NULL);
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test_memprot_get_permissions(false, mem_type, &read_perm_high, &write_perm_high, mem_type == MEMPROT_IRAM0_SRAM ? &exec_perm_high : NULL);
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//get testing pointers for low & high regions
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volatile uint32_t *ptr_low = test_memprot_addr_low(mem_type);
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volatile uint32_t *ptr_high = test_memprot_addr_high(mem_type);
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const uint32_t test_val = 100;
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//temporarily allow WRITE for setting the test values
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esp_memprot_set_monitor_en(mem_type, false);
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test_memprot_set_permissions(true, mem_type, read_perm_low, true, mem_type == MEMPROT_IRAM0_SRAM ? &exec_perm_low : NULL);
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test_memprot_set_permissions(false, mem_type, read_perm_high, true, mem_type == MEMPROT_IRAM0_SRAM ? &exec_perm_high : NULL);
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*ptr_low = test_val;
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*ptr_high = test_val + 1;
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test_memprot_set_permissions(true, mem_type, read_perm_low, write_perm_low, mem_type == MEMPROT_IRAM0_SRAM ? &exec_perm_low : NULL);
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test_memprot_set_permissions(false, mem_type, read_perm_high, write_perm_high, mem_type == MEMPROT_IRAM0_SRAM ? &exec_perm_high : NULL);
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esp_memprot_set_monitor_en(mem_type, true);
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//perform READ test in low region
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esp_rom_printf("%s read low: ", esp_memprot_mem_type_to_str(mem_type));
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esp_memprot_monitor_clear_intr(mem_type);
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volatile uint32_t val = *ptr_low;
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if ( read_perm_low && val != test_val ) {
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esp_rom_printf( "UNEXPECTED VALUE 0x%08X -", val );
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dump_status_register(mem_type);
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} else {
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check_test_result(mem_type, read_perm_low);
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}
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//perform READ in high region
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esp_rom_printf("%s read high: ", esp_memprot_mem_type_to_str(mem_type));
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esp_memprot_monitor_clear_intr(mem_type);
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val = *ptr_high;
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if ( read_perm_high && val != (test_val + 1) ) {
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esp_rom_printf( "UNEXPECTED VALUE 0x%08X -", val);
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dump_status_register(mem_type);
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} else {
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check_test_result(mem_type, read_perm_high);
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}
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}
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static void test_memprot_write(mem_type_prot_t mem_type)
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{
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//get current READ & WRITE permission settings
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bool write_perm_low, write_perm_high, read_perm_low, read_perm_high;
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test_memprot_get_permissions(true, mem_type, &read_perm_low, &write_perm_low, NULL);
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test_memprot_get_permissions(false, mem_type, &read_perm_high, &write_perm_high, NULL);
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//ensure READ enabled
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esp_memprot_set_monitor_en(mem_type, false);
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test_memprot_set_permissions(true, mem_type, true, write_perm_low, NULL);
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test_memprot_set_permissions(false, mem_type, true, write_perm_high, NULL);
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esp_memprot_set_monitor_en(mem_type, true);
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//get testing pointers for low & high regions
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volatile uint32_t *ptr_low = test_memprot_addr_low(mem_type);
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volatile uint32_t *ptr_high = test_memprot_addr_high(mem_type);
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const uint32_t test_val = 10;
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//perform WRITE in low region
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esp_rom_printf("%s write low: ", esp_memprot_mem_type_to_str(mem_type));
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esp_memprot_monitor_clear_intr(mem_type);
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volatile uint32_t val = 0;
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*ptr_low = test_val;
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val = *ptr_low;
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if ( val != test_val && write_perm_low ) {
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esp_rom_printf( "UNEXPECTED VALUE 0x%08X -", val);
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dump_status_register(mem_type);
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} else {
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check_test_result(mem_type, write_perm_low);
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}
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//perform WRITE in high region
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esp_rom_printf("%s write high: ", esp_memprot_mem_type_to_str(mem_type));
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esp_memprot_monitor_clear_intr(mem_type);
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val = 0;
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*ptr_high = test_val + 1;
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val = *ptr_high;
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if ( val != (test_val + 1) && write_perm_high ) {
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esp_rom_printf( "UNEXPECTED VALUE 0x%08X -", val);
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dump_status_register(mem_type);
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} else {
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check_test_result(mem_type, write_perm_high);
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}
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//restore original permissions
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esp_memprot_set_monitor_en(mem_type, false);
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test_memprot_set_permissions(true, mem_type, true, read_perm_low, NULL);
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test_memprot_set_permissions(false, mem_type, true, read_perm_high, NULL);
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esp_memprot_set_monitor_en(mem_type, true);
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}
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static void test_memprot_exec(mem_type_prot_t mem_type)
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{
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if ( mem_type != MEMPROT_IRAM0_SRAM ) {
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esp_rom_printf("Error: EXEC test available only for IRAM access.\n" );
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return;
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}
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bool write_perm_low, write_perm_high, read_perm_low, read_perm_high, exec_perm_low, exec_perm_high;
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//temporarily enable READ/WRITE
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test_memprot_get_permissions(true, mem_type, &read_perm_low, &write_perm_low, &exec_perm_low);
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test_memprot_get_permissions(false, mem_type, &read_perm_high, &write_perm_high, &exec_perm_high);
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esp_memprot_set_monitor_en(mem_type, false);
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test_memprot_set_permissions(true, mem_type, true, true, &exec_perm_low);
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test_memprot_set_permissions(false, mem_type, true, true, &exec_perm_high);
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esp_memprot_set_monitor_en(mem_type, true);
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//get testing pointers for low & high regions, zero 8B slot
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void *fnc_ptr_low = test_memprot_addr_low(mem_type);
|
||||
void *fnc_ptr_high = test_memprot_addr_high(mem_type);
|
||||
memset( fnc_ptr_low, 0, 8);
|
||||
memset( fnc_ptr_high, 0, 8);
|
||||
|
||||
//inject the code to both low & high segments
|
||||
memcpy( (void *)fnc_ptr_low, (const void *)fnc_buff, sizeof(fnc_buff) );
|
||||
memcpy( (void *)fnc_ptr_high, (const void *)fnc_buff, sizeof(fnc_buff) );
|
||||
|
||||
uint32_t res = 0;
|
||||
|
||||
//LOW REGION: clear the intr flag & try to execute the code injected
|
||||
esp_rom_printf("%s exec low: ", esp_memprot_mem_type_to_str(mem_type));
|
||||
esp_memprot_monitor_clear_intr(mem_type);
|
||||
|
||||
fnc_ptr fnc = (fnc_ptr)fnc_ptr_low;
|
||||
|
||||
g_override_illegal_instruction = true;
|
||||
res = fnc( 5 );
|
||||
g_override_illegal_instruction = false;
|
||||
|
||||
//check results
|
||||
bool fnc_call_ok = res == 10;
|
||||
if ( fnc_call_ok ) {
|
||||
check_test_result(mem_type, exec_perm_low);
|
||||
} else {
|
||||
if ( !exec_perm_low ) {
|
||||
check_test_result(mem_type, false);
|
||||
} else {
|
||||
esp_rom_printf(" FAULT [injected code not executed]\n");
|
||||
}
|
||||
}
|
||||
|
||||
//HIGH REGION: clear the intr-on flag & try to execute the code injected
|
||||
esp_rom_printf("%s exec high: ", esp_memprot_mem_type_to_str(mem_type));
|
||||
esp_memprot_monitor_clear_intr(mem_type);
|
||||
|
||||
fnc = (fnc_ptr)fnc_ptr_high;
|
||||
|
||||
g_override_illegal_instruction = true;
|
||||
res = fnc( 6 );
|
||||
g_override_illegal_instruction = false;
|
||||
|
||||
fnc_call_ok = res == 12;
|
||||
if ( fnc_call_ok ) {
|
||||
check_test_result(mem_type, exec_perm_high);
|
||||
} else {
|
||||
if ( !exec_perm_high ) {
|
||||
check_test_result(mem_type, false);
|
||||
} else {
|
||||
esp_rom_printf(" FAULT [injected code not executed]\n");
|
||||
}
|
||||
}
|
||||
|
||||
//restore original permissions
|
||||
esp_memprot_set_monitor_en(mem_type, false);
|
||||
test_memprot_set_permissions(true, mem_type, read_perm_low, write_perm_low, &exec_perm_low);
|
||||
test_memprot_set_permissions(false, mem_type, read_perm_high, write_perm_high, &exec_perm_high);
|
||||
esp_memprot_set_monitor_en(mem_type, true);
|
||||
}
|
||||
|
||||
|
||||
/* ********************************************************************************************
|
||||
* main test runner
|
||||
*/
|
||||
void app_main(void)
|
||||
{
|
||||
esp_memprot_set_prot_int(false, false, NULL, NULL);
|
||||
|
||||
test_memprot_read(MEMPROT_IRAM0_SRAM);
|
||||
test_memprot_write(MEMPROT_IRAM0_SRAM);
|
||||
test_memprot_exec(MEMPROT_IRAM0_SRAM);
|
||||
|
||||
test_memprot_read(MEMPROT_DRAM0_SRAM);
|
||||
test_memprot_write(MEMPROT_DRAM0_SRAM);
|
||||
}
|
||||
52
tools/test_apps/system/memprot/main/esp32c3/test_panic.c
Normal file
52
tools/test_apps/system/memprot/main/esp32c3/test_panic.c
Normal file
@@ -0,0 +1,52 @@
|
||||
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "riscv/rvruntime-frames.h"
|
||||
#include "esp_private/panic_internal.h"
|
||||
|
||||
#define MCAUSE_ILLEGAL_INSTRUCTION 2
|
||||
|
||||
extern void esp_panic_handler(panic_info_t *info);
|
||||
volatile bool g_override_illegal_instruction = false;
|
||||
|
||||
void __real_esp_panic_handler(panic_info_t *info);
|
||||
|
||||
void return_from_panic_handler(RvExcFrame *frm) __attribute__((noreturn));
|
||||
|
||||
/* Memprot test specific IllegalInstruction exception handler:
|
||||
* when testing the protection against a code execution, sample code
|
||||
* is being injected into various memory regions which produces
|
||||
* Illegal instruction on execution attempt. Such a result is expected
|
||||
* but it causes system reboot in the standard panic handler.
|
||||
* The following variant of panic handling simply returns back to the
|
||||
* next instruction and continues normal execution.
|
||||
*
|
||||
* NOTE: if Illegal instruction comes from a different source than the testing code
|
||||
* the behavior is undefined
|
||||
* */
|
||||
void __wrap_esp_panic_handler(panic_info_t *info)
|
||||
{
|
||||
RvExcFrame *frm = (RvExcFrame *)info->frame;
|
||||
if ( frm->mcause == MCAUSE_ILLEGAL_INSTRUCTION && g_override_illegal_instruction == true ) {
|
||||
/* Return from exception to the return address that called the faulting function.
|
||||
*/
|
||||
frm->mepc = frm->ra;
|
||||
|
||||
/* Restore the CPU state and return from the exception.
|
||||
*/
|
||||
return_from_panic_handler(frm);
|
||||
} else {
|
||||
__real_esp_panic_handler(info);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user