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re-enable riscv ulp gpio support and examples

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Closes https://github.com/espressif/esp-idf/issues/8691
Closes https://github.com/espressif/esp-idf/issues/9094
This commit is contained in:
Marius Vikhammer
2022-05-26 11:30:31 +08:00
parent 9c4a12b11e
commit 6e79cc69f9
16 changed files with 62 additions and 58 deletions
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5
examples/system/ulp_riscv/gpio_interrupt/README.md
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@@ -1,6 +1,5 @@
| Supported Targets | ESP32-S2 |
| ----------------- | -------- |
| Supported Targets | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- |
# ULP-RISC-V simple example with GPIO Interrupt:
This example demonstrates how to program the ULP-RISC-V coprocessor to wake up from a RTC IO interrupt, instead of waking periodically from the ULP timer.