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gdma: separate tx/rx channel interrupt

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This commit is contained in:
morris
2021-04-27 18:52:42 +08:00
parent 58490418ad
commit 6e981af406
11 changed files with 283 additions and 152 deletions
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9
components/soc/esp32c3/gdma_periph.c
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@@ -20,13 +20,16 @@ const gdma_signal_conn_t gdma_periph_signals = {
.module = PERIPH_GDMA_MODULE,
.pairs = {
[0] = {
.irq_id = ETS_DMA_CH0_INTR_SOURCE
.rx_irq_id = ETS_DMA_CH0_INTR_SOURCE,
.tx_irq_id = ETS_DMA_CH0_INTR_SOURCE,
},
[1] = {
.irq_id = ETS_DMA_CH1_INTR_SOURCE
.rx_irq_id = ETS_DMA_CH1_INTR_SOURCE,
.tx_irq_id = ETS_DMA_CH1_INTR_SOURCE,
},
[2] = {
.irq_id = ETS_DMA_CH2_INTR_SOURCE
.rx_irq_id = ETS_DMA_CH2_INTR_SOURCE,
.tx_irq_id = ETS_DMA_CH2_INTR_SOURCE,
}
}
}

7
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -14,7 +14,6 @@
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
@@ -68,8 +67,9 @@
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_GDMA_GROUPS (1)
#define SOC_GDMA_PAIRS_PER_GROUP (3)
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C3 has 1 GPIO peripheral
@@ -205,6 +205,7 @@
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units
#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units