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https://github.com/espressif/esp-idf.git
synced 2025-08-09 20:41:14 +00:00
gdma: separate tx/rx channel interrupt
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@@ -20,19 +20,24 @@ const gdma_signal_conn_t gdma_periph_signals = {
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.module = PERIPH_GDMA_MODULE,
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.pairs = {
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[0] = {
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.irq_id = ETS_DMA_CH0_INTR_SOURCE
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.rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE,
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},
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[1] = {
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.irq_id = ETS_DMA_CH1_INTR_SOURCE
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.rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE,
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},
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[2] = {
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.irq_id = ETS_DMA_CH2_INTR_SOURCE
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.rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE,
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},
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[3] = {
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.irq_id = ETS_DMA_CH3_INTR_SOURCE
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.rx_irq_id = ETS_DMA_IN_CH3_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH3_INTR_SOURCE,
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},
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[4] = {
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.irq_id = ETS_DMA_CH4_INTR_SOURCE
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.rx_irq_id = ETS_DMA_IN_CH4_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH4_INTR_SOURCE,
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}
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}
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}
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@@ -1,20 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#define SOC_GDMA_GROUPS (1)
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#define SOC_GDMA_PAIRS_PER_GROUP (5)
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#define SOC_GDMA_L2_FIFO_BASE_SIZE (16)
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#define SOC_GDMA_SUPPORT_EXTMEM (1)
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@@ -124,16 +124,16 @@ typedef enum {
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ETS_DCACHE_SYNC0_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/
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ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/
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ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
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ETS_DMA_CH0_INTR_SOURCE, /**< interrupt of general DMA channel 0, LEVEL*/
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ETS_DMA_CH1_INTR_SOURCE, /**< interrupt of general DMA channel 1, LEVEL*/
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ETS_DMA_CH2_INTR_SOURCE, /**< interrupt of general DMA channel 2, LEVEL*/
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ETS_DMA_CH3_INTR_SOURCE, /**< interrupt of general DMA channel 3, LEVEL*/
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ETS_DMA_CH4_INTR_SOURCE, /**< interrupt of general DMA channel 4, LEVEL*/
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ETS_DMA_OUT_CH0_INTR_SOURCE,
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ETS_DMA_OUT_CH1_INTR_SOURCE,
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ETS_DMA_OUT_CH2_INTR_SOURCE,
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ETS_DMA_OUT_CH3_INTR_SOURCE,
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ETS_DMA_OUT_CH4_INTR_SOURCE,
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ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA RX channel 0, LEVEL*/
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ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA RX channel 1, LEVEL*/
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ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA RX channel 2, LEVEL*/
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ETS_DMA_IN_CH3_INTR_SOURCE, /**< interrupt of general DMA RX channel 3, LEVEL*/
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ETS_DMA_IN_CH4_INTR_SOURCE, /**< interrupt of general DMA RX channel 4, LEVEL*/
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ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA TX channel 0, LEVEL*/
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ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA TX channel 1, LEVEL*/
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ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA TX channel 2, LEVEL*/
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ETS_DMA_OUT_CH3_INTR_SOURCE, /**< interrupt of general DMA TX channel 3, LEVEL*/
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ETS_DMA_OUT_CH4_INTR_SOURCE, /**< interrupt of general DMA TX channel 4, LEVEL*/
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ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
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ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
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ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
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@@ -33,7 +33,10 @@
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#include "cpu_caps.h"
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/*-------------------------- GDMA CAPS ---------------------------------------*/
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#include "gdma_caps.h"
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#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
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#define SOC_GDMA_PAIRS_PER_GROUP (5) // Number of GDMA pairs in each group
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#define SOC_GDMA_L2_FIFO_BASE_SIZE (16) // Basic size of GDMA Level 2 FIFO
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#define SOC_GDMA_SUPPORT_EXTMEM (1) // GDMA can access external PSRAM
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/*-------------------------- GPIO CAPS ---------------------------------------*/
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#include "gpio_caps.h"
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