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feat(parlio_tx): support cs signal on esp32c5 v1.0

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Chen Jichang
2025-04-24 13:51:49 +08:00
parent 182b33efb2
commit 6edf48d253
19 changed files with 221 additions and 32 deletions
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17
components/hal/esp32c6/include/hal/parlio_ll.h
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@@ -509,6 +509,23 @@ static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en)
dev->tx_cfg0.tx_hw_valid_en = en;
}
/**
* @brief Set TX valid signal delay
*
* @param dev Parallel IO register base address
* @param start_delay Number of clock cycles to delay
* @param stop_delay Number of clock cycles to delay
* @return true: success, false: valid delay is not supported
*/
static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t start_delay, uint32_t stop_delay)
{
(void)dev;
if (start_delay == 0 && stop_delay == 0) {
return true;
}
return false;
}
/**
* @brief Set the sample clock edge
*