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Merge branch 'bugfix/gpio_pin_num_fix_v4.3' into 'release/v4.3'

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gpio: Fix some gpio pin num errors on esp32s2 and esp32c3 (backport v4.3)

See merge request espressif/esp-idf!17109
This commit is contained in:
Michael (XIAO Xufeng)
2022-02-23 03:28:15 +00:00
parent 1674c63f82 b1017de2e6
commit 6f99b8da73
7 changed files with 16 additions and 29 deletions
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8
components/driver/test/test_gpio.c
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@@ -39,12 +39,12 @@
#define TEST_GPIO_EXT_IN_IO 20 // default input GPIO
#define TEST_GPIO_OUTPUT_PIN 12
#define TEST_GPIO_INPUT_ONLY_PIN 46
#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_47
#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_MAX
#elif CONFIG_IDF_TARGET_ESP32C3
#define TEST_GPIO_EXT_OUT_IO 2 // default output GPIO
#define TEST_GPIO_EXT_IN_IO 3 // default input GPIO
#define TEST_GPIO_OUTPUT_PIN 1
#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_21
#define TEST_GPIO_OUTPUT_MAX GPIO_NUM_MAX
#endif
// define public test io on all boards(esp32, esp32s2, esp32s3, esp32c3)
@@ -744,11 +744,11 @@ static void gpio_isr_handler(void* arg)
*/
TEST_CASE("GPIO ISR service test", "[gpio][ignore]")
{
static gpio_isr_param_t io9_param = {
gpio_isr_param_t io9_param = {
.gpio_num = TEST_IO_9,
.isr_cnt = 0,
};
static gpio_isr_param_t io10_param = {
gpio_isr_param_t io10_param = {
.gpio_num = TEST_IO_10,
.isr_cnt = 0,
};

15
components/hal/esp32c3/include/hal/gpio_ll.h
View File

@@ -26,6 +26,7 @@
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/usb_serial_jtag_reg.h"
#include "hal/gpio_types.h"
#include "stdlib.h"
@@ -33,17 +34,6 @@
extern "C" {
#endif
/*
* The following defines are used to disable USB JTAG when pins 18 and pins 19
* are set to be used as GPIO.
* See gpio_pad_select_gpio() below.
*
* TODO: Delete these definitions once the USB device registers definition is
* merged.
*/
#define USB_DEVICE_CONF0_REG (0x60043018)
#define USB_DEVICE_USB_PAD_ENABLE (BIT(14))
// Get GPIO hardware instance with giving gpio num
#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
@@ -400,8 +390,9 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
// Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
}
PIN_FUNC_SELECT(pin_name, func);
}

1
components/hal/include/hal/gpio_types.h
View File

@@ -295,7 +295,6 @@ typedef enum {
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
GPIO_NUM_MAX,
/** @endcond */
} gpio_num_t;

6
components/soc/esp32c3/include/soc/io_mux_reg.h
View File

@@ -141,9 +141,9 @@
#define SD_DATA2_GPIO_NUM 9
#define SD_DATA3_GPIO_NUM 10
#define MAX_RTC_GPIO_NUM 0
#define MAX_PAD_GPIO_NUM 22
#define MAX_GPIO_NUM 22
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 21
#define MAX_GPIO_NUM 25
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)

2
components/soc/esp32s2/gpio_periph.c
View File

@@ -62,7 +62,6 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO44_REG,
IO_MUX_GPIO45_REG,
IO_MUX_GPIO46_REG,
0,
};
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
@@ -113,5 +112,4 @@ const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
BIT(23),
BIT(24),
BIT(25),
BIT(26),
};

12
components/soc/esp32s2/include/soc/soc_caps.h
View File

@@ -94,18 +94,18 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-S2 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PIN_COUNT (48)
#define SOC_GPIO_PIN_COUNT (47)
// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2 those PADs which have RTC functions must set pullup/down/capability via RTC register.
// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-S2
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// 0~47 except from 22~25, 47 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47))
// GPIO 46, 47 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47))
// 0~46 except from 22~25 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0x7FFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
// GPIO 46 is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46))
// Support to configure slept status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)

1
components/soc/esp32s2/rtc_io_periph.c
View File

@@ -62,7 +62,6 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-1,//GPIO44
-1,//GPIO45
-1,//GPIO46
-1,//GPIO47
};
//Reg,Mux,Fun,IE,Up,Down,Rtc_number