alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-09-30 19:19:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat(sdmmc): supported sd2.0 on esp32p4

Browse Source
This commit is contained in:
Armando
2023-08-29 19:50:27 +08:00
committed by Armando (Dou Yiwen)
parent 1685dbc985
commit 70314b56d5
39 changed files with 2255 additions and 565 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -139,6 +139,10 @@ config SOC_PSRAM_DMA_CAPABLE
bool
default y
config SOC_SDMMC_HOST_SUPPORTED
bool
default y
config SOC_WDT_SUPPORTED
bool
default y
@@ -763,6 +767,22 @@ config SOC_RSA_MAX_BIT_LEN
int
default 4096
config SOC_SDMMC_USE_IOMUX
bool
default y
config SOC_SDMMC_USE_GPIO_MATRIX
bool
default y
config SOC_SDMMC_NUM_SLOTS
int
default 2
config SOC_SDMMC_DELAY_PHASE_NUM
int
default 4
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
@@ -795,26 +815,6 @@ config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
bool
default y
config SOC_SDMMC_USE_IOMUX
bool
default y
config SOC_SDMMC_USE_GPIO_MATRIX
bool
default y
config SOC_SDMMC_NUM_SLOTS
int
default 2
config SOC_SDMMC_IOMUX_FUNC
bool
default n
config SOC_SDMMC_DMA_NEED_CACHE_WB
bool
default y
config SOC_SDM_GROUPS
int
default 1

17
components/soc/esp32p4/include/soc/clk_tree_defs.h
View File

@@ -143,6 +143,7 @@ typedef enum {
// For digital domain: peripherals
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from SPLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from SPLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F200M, /*!< PLL_F200M_CLK is derived from SPLL (clock gating + fixed divider of 3), it has a fixed frequency of 200MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from SPLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
SOC_MOD_CLK_CPLL, /*!< CPLL is from 40MHz XTAL oscillator frequency multipliers, it has a fixed frequency of 400MHz */
SOC_MOD_CLK_SPLL, /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, it has a fixed frequency of 480MHz */
@@ -522,6 +523,22 @@ typedef enum {
#endif
} soc_periph_parlio_clk_src_t;
//////////////////////////////////////////////////SDMMC///////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDMMC
*/
#define SOC_SDMMC_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_PLL_F200M}
/**
* @brief Type of SDMMC clock source
*/
typedef enum {
SDMMC_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the default choice */
SDMMC_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_160M as the source clock */
SDMMC_CLK_SRC_PLL200M = SOC_MOD_CLK_PLL_F200M, /*!< Select PLL_200M as the source clock */
} soc_periph_sdmmc_clk_src_t;
#ifdef __cplusplus
}
#endif

2
components/soc/esp32p4/include/soc/lp_clkrst_struct.h
View File

@@ -785,6 +785,8 @@ typedef struct {
volatile lp_clkrst_date_reg_t date;
} lp_clkrst_dev_t;
extern lp_clkrst_dev_t LP_AON_CLKRST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");

14
components/soc/esp32p4/include/soc/sdmmc_pins.h
View File

@@ -5,3 +5,17 @@
*/
#pragma once
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK 43
#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD 44
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0 39
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1 40
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2 41
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3 42
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4 45
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5 46
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6 47
#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7 48
#define SDMMC_SLOT0_FUNC 0
// SLOT1 doesn't go through IOMUX

128
components/soc/esp32p4/include/soc/sdmmc_reg.h
View File

@@ -163,7 +163,7 @@ extern "C" {
* Clock source selection register
*/
#define SDHOST_CLKSRC_REG (DR_REG_SDHOST_BASE + 0xc)
/** SDHOST_CLKSRC_REG : R/W; bitpos: [3:0]; default: 0;
/** SDHOST_CLKSRC : R/W; bitpos: [3:0]; default: 0;
* Clock divider source for two SD cards is supported. Each card has two bits assigned
* to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for
* card 1. Card 0 maps and internally routes clock divider[0:3] outputs to
@@ -173,10 +173,10 @@ extern "C" {
* 10 : Clock divider 2;
* 11 : Clock divider 3.
*/
#define SDHOST_CLKSRC_REG 0x0000000FU
#define SDHOST_CLKSRC_REG_M (SDHOST_CLKSRC_REG_V << SDHOST_CLKSRC_REG_S)
#define SDHOST_CLKSRC_REG_V 0x0000000FU
#define SDHOST_CLKSRC_REG_S 0
#define SDHOST_CLKSRC 0x0000000FU
#define SDHOST_CLKSRC_M (SDHOST_CLKSRC_V << SDHOST_CLKSRC_S)
#define SDHOST_CLKSRC_V 0x0000000FU
#define SDHOST_CLKSRC_S 0
/** SDHOST_CLKENA_REG register
* Clock enable register
@@ -321,13 +321,13 @@ extern "C" {
* Command argument data register
*/
#define SDHOST_CMDARG_REG (DR_REG_SDHOST_BASE + 0x28)
/** SDHOST_CMDARG_REG : R/W; bitpos: [31:0]; default: 0;
/** SDHOST_CMDARG : R/W; bitpos: [31:0]; default: 0;
* Value indicates command argument to be passed to the card.
*/
#define SDHOST_CMDARG_REG 0xFFFFFFFFU
#define SDHOST_CMDARG_REG_M (SDHOST_CMDARG_REG_V << SDHOST_CMDARG_REG_S)
#define SDHOST_CMDARG_REG_V 0xFFFFFFFFU
#define SDHOST_CMDARG_REG_S 0
#define SDHOST_CMDARG 0xFFFFFFFFU
#define SDHOST_CMDARG_M (SDHOST_CMDARG_V << SDHOST_CMDARG_S)
#define SDHOST_CMDARG_V 0xFFFFFFFFU
#define SDHOST_CMDARG_S 0
/** SDHOST_CMD_REG register
* Command and boot configuration register
@@ -808,25 +808,25 @@ extern "C" {
* Transferred byte count register
*/
#define SDHOST_TCBCNT_REG (DR_REG_SDHOST_BASE + 0x5c)
/** SDHOST_TCBCNT_REG : RO; bitpos: [31:0]; default: 0;
/** SDHOST_TCBCNT : RO; bitpos: [31:0]; default: 0;
* Number of bytes transferred by CIU unit to card.
*/
#define SDHOST_TCBCNT_REG 0xFFFFFFFFU
#define SDHOST_TCBCNT_REG_M (SDHOST_TCBCNT_REG_V << SDHOST_TCBCNT_REG_S)
#define SDHOST_TCBCNT_REG_V 0xFFFFFFFFU
#define SDHOST_TCBCNT_REG_S 0
#define SDHOST_TCBCNT 0xFFFFFFFFU
#define SDHOST_TCBCNT_M (SDHOST_TCBCNT_V << SDHOST_TCBCNT_S)
#define SDHOST_TCBCNT_V 0xFFFFFFFFU
#define SDHOST_TCBCNT_S 0
/** SDHOST_TBBCNT_REG register
* Transferred byte count register
*/
#define SDHOST_TBBCNT_REG (DR_REG_SDHOST_BASE + 0x60)
/** SDHOST_TBBCNT_REG : RO; bitpos: [31:0]; default: 0;
/** SDHOST_TBBCNT : RO; bitpos: [31:0]; default: 0;
* Number of bytes transferred between Host/DMA memory and BIU FIFO.
*/
#define SDHOST_TBBCNT_REG 0xFFFFFFFFU
#define SDHOST_TBBCNT_REG_M (SDHOST_TBBCNT_REG_V << SDHOST_TBBCNT_REG_S)
#define SDHOST_TBBCNT_REG_V 0xFFFFFFFFU
#define SDHOST_TBBCNT_REG_S 0
#define SDHOST_TBBCNT 0xFFFFFFFFU
#define SDHOST_TBBCNT_M (SDHOST_TBBCNT_V << SDHOST_TBBCNT_S)
#define SDHOST_TBBCNT_V 0xFFFFFFFFU
#define SDHOST_TBBCNT_S 0
/** SDHOST_DEBNCE_REG register
* Debounce filter time configuration register
@@ -846,26 +846,26 @@ extern "C" {
* User ID (scratchpad) register
*/
#define SDHOST_USRID_REG (DR_REG_SDHOST_BASE + 0x68)
/** SDHOST_USRID_REG : R/W; bitpos: [31:0]; default: 0;
/** SDHOST_USRID : R/W; bitpos: [31:0]; default: 0;
* User identification register, value set by user. Can also be used as a scratchpad
* register by user.
*/
#define SDHOST_USRID_REG 0xFFFFFFFFU
#define SDHOST_USRID_REG_M (SDHOST_USRID_REG_V << SDHOST_USRID_REG_S)
#define SDHOST_USRID_REG_V 0xFFFFFFFFU
#define SDHOST_USRID_REG_S 0
#define SDHOST_USRID 0xFFFFFFFFU
#define SDHOST_USRID_M (SDHOST_USRID_V << SDHOST_USRID_S)
#define SDHOST_USRID_V 0xFFFFFFFFU
#define SDHOST_USRID_S 0
/** SDHOST_VERID_REG register
* Version ID (scratchpad) register
*/
#define SDHOST_VERID_REG (DR_REG_SDHOST_BASE + 0x6c)
/** SDHOST_VERSIONID_REG : RO; bitpos: [31:0]; default: 1412572938;
/** SDHOST_VERSIONID : RO; bitpos: [31:0]; default: 1412572938;
* Hardware version register. Can also be read by fireware.
*/
#define SDHOST_VERSIONID_REG 0xFFFFFFFFU
#define SDHOST_VERSIONID_REG_M (SDHOST_VERSIONID_REG_V << SDHOST_VERSIONID_REG_S)
#define SDHOST_VERSIONID_REG_V 0xFFFFFFFFU
#define SDHOST_VERSIONID_REG_S 0
#define SDHOST_VERSIONID 0xFFFFFFFFU
#define SDHOST_VERSIONID_M (SDHOST_VERSIONID_V << SDHOST_VERSIONID_S)
#define SDHOST_VERSIONID_V 0xFFFFFFFFU
#define SDHOST_VERSIONID_S 0
/** SDHOST_HCON_REG register
* Hardware feature register
@@ -1036,15 +1036,15 @@ extern "C" {
* Descriptor base address register
*/
#define SDHOST_DBADDR_REG (DR_REG_SDHOST_BASE + 0x88)
/** SDHOST_DBADDR_REG : R/W; bitpos: [31:0]; default: 0;
/** SDHOST_DBADDR : R/W; bitpos: [31:0]; default: 0;
* Start of Descriptor List. Contains the base address of the First Descriptor. The
* LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence
* these LSB bits may be treated as read-only.
*/
#define SDHOST_DBADDR_REG 0xFFFFFFFFU
#define SDHOST_DBADDR_REG_M (SDHOST_DBADDR_REG_V << SDHOST_DBADDR_REG_S)
#define SDHOST_DBADDR_REG_V 0xFFFFFFFFU
#define SDHOST_DBADDR_REG_S 0
#define SDHOST_DBADDR 0xFFFFFFFFU
#define SDHOST_DBADDR_M (SDHOST_DBADDR_V << SDHOST_DBADDR_S)
#define SDHOST_DBADDR_V 0xFFFFFFFFU
#define SDHOST_DBADDR_S 0
/** SDHOST_IDSTS_REG register
* IDMAC status register
@@ -1220,29 +1220,29 @@ extern "C" {
* Host descriptor address pointer
*/
#define SDHOST_DSCADDR_REG (DR_REG_SDHOST_BASE + 0x94)
/** SDHOST_DSCADDR_REG : RO; bitpos: [31:0]; default: 0;
/** SDHOST_DSCADDR : RO; bitpos: [31:0]; default: 0;
* Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on
* reset. This register points to the start address of the current descriptor read by
* the IDMAC.
*/
#define SDHOST_DSCADDR_REG 0xFFFFFFFFU
#define SDHOST_DSCADDR_REG_M (SDHOST_DSCADDR_REG_V << SDHOST_DSCADDR_REG_S)
#define SDHOST_DSCADDR_REG_V 0xFFFFFFFFU
#define SDHOST_DSCADDR_REG_S 0
#define SDHOST_DSCADDR 0xFFFFFFFFU
#define SDHOST_DSCADDR_M (SDHOST_DSCADDR_V << SDHOST_DSCADDR_S)
#define SDHOST_DSCADDR_V 0xFFFFFFFFU
#define SDHOST_DSCADDR_S 0
/** SDHOST_BUFADDR_REG register
* Host buffer address pointer register
*/
#define SDHOST_BUFADDR_REG (DR_REG_SDHOST_BASE + 0x98)
/** SDHOST_BUFADDR_REG : RO; bitpos: [31:0]; default: 0;
/** SDHOST_BUFADDR : RO; bitpos: [31:0]; default: 0;
* Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
* reset. This register points to the current Data Buffer Address being accessed by
* the IDMAC.
*/
#define SDHOST_BUFADDR_REG 0xFFFFFFFFU
#define SDHOST_BUFADDR_REG_M (SDHOST_BUFADDR_REG_V << SDHOST_BUFADDR_REG_S)
#define SDHOST_BUFADDR_REG_V 0xFFFFFFFFU
#define SDHOST_BUFADDR_REG_S 0
#define SDHOST_BUFADDR 0xFFFFFFFFU
#define SDHOST_BUFADDR_M (SDHOST_BUFADDR_V << SDHOST_BUFADDR_S)
#define SDHOST_BUFADDR_V 0xFFFFFFFFU
#define SDHOST_BUFADDR_S 0
/** SDHOST_CARDTHRCTL_REG register
* Card Threshold Control register
@@ -1328,14 +1328,14 @@ extern "C" {
* CPU write and read transmit data by FIFO
*/
#define SDHOST_BUFFIFO_REG (DR_REG_SDHOST_BASE + 0x200)
/** SDHOST_BUFFIFO_REG : R/W; bitpos: [31:0]; default: 0;
/** SDHOST_BUFFIFO : R/W; bitpos: [31:0]; default: 0;
* CPU write and read transmit data by FIFO. This register points to the current Data
* FIFO .
*/
#define SDHOST_BUFFIFO_REG 0xFFFFFFFFU
#define SDHOST_BUFFIFO_REG_M (SDHOST_BUFFIFO_REG_V << SDHOST_BUFFIFO_REG_S)
#define SDHOST_BUFFIFO_REG_V 0xFFFFFFFFU
#define SDHOST_BUFFIFO_REG_S 0
#define SDHOST_BUFFIFO 0xFFFFFFFFU
#define SDHOST_BUFFIFO_M (SDHOST_BUFFIFO_V << SDHOST_BUFFIFO_S)
#define SDHOST_BUFFIFO_V 0xFFFFFFFFU
#define SDHOST_BUFFIFO_S 0
/** SDHOST_CLK_EDGE_SEL_REG register
* SDIO control register.
@@ -1493,6 +1493,34 @@ extern "C" {
#define SDHOST_DLL_CAL_END_V 0x00000001U
#define SDHOST_DLL_CAL_END_S 1
#define SDMMC_INTMASK_IO_SLOT1 BIT(17)
#define SDMMC_INTMASK_IO_SLOT0 BIT(16)
#define SDMMC_INTMASK_EBE BIT(15)
#define SDMMC_INTMASK_ACD BIT(14)
#define SDMMC_INTMASK_SBE BIT(13)
#define SDMMC_INTMASK_HLE BIT(12)
#define SDMMC_INTMASK_FRUN BIT(11)
#define SDMMC_INTMASK_HTO BIT(10)
#define SDMMC_INTMASK_DTO BIT(9)
#define SDMMC_INTMASK_RTO BIT(8)
#define SDMMC_INTMASK_DCRC BIT(7)
#define SDMMC_INTMASK_RCRC BIT(6)
#define SDMMC_INTMASK_RXDR BIT(5)
#define SDMMC_INTMASK_TXDR BIT(4)
#define SDMMC_INTMASK_DATA_OVER BIT(3)
#define SDMMC_INTMASK_CMD_DONE BIT(2)
#define SDMMC_INTMASK_RESP_ERR BIT(1)
#define SDMMC_INTMASK_CD BIT(0)
#define SDMMC_IDMAC_INTMASK_AI BIT(9)
#define SDMMC_IDMAC_INTMASK_NI BIT(8)
#define SDMMC_IDMAC_INTMASK_CES BIT(5)
#define SDMMC_IDMAC_INTMASK_DU BIT(4)
#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
#define SDMMC_IDMAC_INTMASK_RI BIT(1)
#define SDMMC_IDMAC_INTMASK_TI BIT(0)
#ifdef __cplusplus
}
#endif

185
components/soc/esp32p4/include/soc/sdmmc_struct.h
View File

@@ -10,6 +10,42 @@
extern "C" {
#endif
typedef struct sdmmc_desc_s {
struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
};
struct {
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
};
void* buffer1_ptr;
union {
void* buffer2_ptr;
void* next_desc_ptr;
};
/**
* These `reserved[12]` are for cache alignment. On P4, L1 Cache alignment is 64B.
* For those who want to access the DMA descriptor in a non-cacheable way, you can
* consider remove these `reserved[12]` bytes.
*/
uint32_t reserved[12];
} sdmmc_desc_t;
#define SDMMC_DMA_MAX_BUF_LEN 4096
#ifndef __cplusplus
_Static_assert(sizeof(sdmmc_desc_t) == 64, "invalid size of sdmmc_desc_t structure");
#endif
/** Group: Control register */
/** Type of ctrl register
* Control register
@@ -39,7 +75,7 @@ typedef union {
* Global interrupt enable/disable bit. 0: Disable; 1: Enable.
*/
uint32_t int_enable:1;
uint32_t reserved_5:1;
uint32_t dma_enable:1;
/** read_wait : R/W; bitpos: [6]; default: 0;
* For sending read-wait to SDIO cards.
*/
@@ -90,7 +126,12 @@ typedef union {
* then software should set this bit.
*/
uint32_t ceata_device_interrupt_status:1;
uint32_t reserved_12:20;
uint32_t reserved2:4;
uint32_t card_voltage_a:4;
uint32_t card_voltage_b:4;
uint32_t enable_od_pullup:1;
uint32_t use_internal_dma:1;
uint32_t reserved3:6;
};
uint32_t val;
} sdhost_ctrl_reg_t;
@@ -147,7 +188,8 @@ typedef union {
* 10 : Clock divider 2;
* 11 : Clock divider 3.
*/
uint32_t clksrc_reg:4;
uint32_t card0:2;
uint32_t card1:2;
uint32_t reserved_4:28;
};
uint32_t val;
@@ -211,21 +253,21 @@ typedef union {
*/
typedef union {
struct {
/** card_width4 : R/W; bitpos: [1:0]; default: 0;
/** card_width : R/W; bitpos: [1:0]; default: 0;
* One bit per card indicates if card is 1-bit or 4-bit mode.
* 0: 1-bit mode;
* 1: 4-bit mode.
* Bit[1:0] correspond to card[1:0] respectively.
*/
uint32_t card_width4:2;
uint32_t card_width:2;
uint32_t reserved_2:14;
/** card_width8 : R/W; bitpos: [17:16]; default: 0;
/** card_width_8 : R/W; bitpos: [17:16]; default: 0;
* One bit per card indicates if card is in 8-bit mode.
* 0: Non 8-bit mode;
* 1: 8-bit mode.
* Bit[17:16] correspond to card[1:0] respectively.
*/
uint32_t card_width8:2;
uint32_t card_width_8:2;
uint32_t reserved_18:14;
};
uint32_t val;
@@ -305,21 +347,6 @@ typedef union {
} sdhost_intmask_reg_t;
/** Group: Command argument data register */
/** Type of cmdarg register
* Command argument data register
*/
typedef union {
struct {
/** cmdarg_reg : R/W; bitpos: [31:0]; default: 0;
* Value indicates command argument to be passed to the card.
*/
uint32_t cmdarg_reg:32;
};
uint32_t val;
} sdhost_cmdarg_reg_t;
/** Group: Command and boot configuration register */
/** Type of cmd register
* Command and boot configuration register
@@ -334,10 +361,10 @@ typedef union {
* 0: No response expected from card; 1: Response expected from card.
*/
uint32_t response_expect:1;
/** response_length : R/W; bitpos: [7]; default: 0;
/** response_long : R/W; bitpos: [7]; default: 0;
* 0: Short response expected from card; 1: Long response expected from card.
*/
uint32_t response_length:1;
uint32_t response_long:1;
/** check_response_crc : R/W; bitpos: [8]; default: 0;
* 0: Do not check; 1: Check response CRC.
* Some of command responses do not return valid CRC bits. Software should disable CRC
@@ -348,11 +375,11 @@ typedef union {
* 0: No data transfer expected; 1: Data transfer expected.
*/
uint32_t data_expected:1;
/** read_write : R/W; bitpos: [10]; default: 0;
/** rw : R/W; bitpos: [10]; default: 0;
* 0: Read from card; 1: Write to card.
* Don't care if no data is expected from card.
*/
uint32_t read_write:1;
uint32_t rw:1;
/** transfer_mode : R/W; bitpos: [11]; default: 0;
* 0: Block data transfer command; 1: Stream data transfer command.
* Don't care if no data expected.
@@ -363,14 +390,14 @@ typedef union {
* end of data transfer.
*/
uint32_t send_auto_stop:1;
/** wait_prvdata_complete : R/W; bitpos: [13]; default: 0;
/** wait_complete : R/W; bitpos: [13]; default: 0;
* 0: Send command at once, even if previous data transfer has not completed; 1: Wait
* for previous data transfer to complete before sending Command.
* The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of
* The SDHOST_WAIT_COMPLETE] = 0 option is typically used to query status of
* card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr
* should be same as in previous command.
*/
uint32_t wait_prvdata_complete:1;
uint32_t wait_complete:1;
/** stop_abort_cmd : R/W; bitpos: [14]; default: 0;
* 0: Neither stop nor abort command can stop current data transfer. If abort is sent
* to function-number currently selected or not in data-transfer mode, then bit should
@@ -381,20 +408,20 @@ typedef union {
* state-machines of CIU can return correctly to idle state.
*/
uint32_t stop_abort_cmd:1;
/** send_initialization : R/W; bitpos: [15]; default: 0;
/** send_init : R/W; bitpos: [15]; default: 0;
* 0: Do not send initialization sequence (80 clocks of 1) before sending this
* command; 1: Send initialization sequence before sending this command.
* After powered on, 80 clocks must be sent to card for initialization before sending
* any commands to card. Bit should be set while sending first command to card so that
* controller will initialize clocks before sending command to card.
*/
uint32_t send_initialization:1;
/** card_number : R/W; bitpos: [20:16]; default: 0;
uint32_t send_init:1;
/** card_num : R/W; bitpos: [20:16]; default: 0;
* Card number in use. Represents physical slot number of card being accessed. In
* SD-only mode, up to two cards are supported.
*/
uint32_t card_number:5;
/** update_clock_registers_only : R/W; bitpos: [21]; default: 0;
uint32_t card_num:5;
/** update_clk_reg : R/W; bitpos: [21]; default: 0;
* 0: Normal command sequence; 1: Do not send commands, just update clock register
* value into card clock domain.
* Following register values are transferred into card clock domain: CLKDIV, CLRSRC,
@@ -407,7 +434,7 @@ typedef union {
* register values for new command sequence to card(s). When bit is set, there are no
* Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
*/
uint32_t update_clock_registers_only:1;
uint32_t update_clk_reg:1;
/** read_ceata_device : R/W; bitpos: [22]; default: 0;
* Read access flag.
* 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;
@@ -437,16 +464,16 @@ typedef union {
* 0: CMD and DATA sent to card bypassing HOLD Register;
* 1: CMD and DATA sent to card through the HOLD Register.
*/
uint32_t use_hole_reg:1;
uint32_t use_hold_reg:1;
uint32_t reserved_30:1;
/** start_cmd : R/W; bitpos: [31]; default: 0;
/** start_command : R/W; bitpos: [31]; default: 0;
* Start command. Once command is served by the CIU, this bit is automatically
* cleared. When this bit is set, host should not attempt to write to any command
* registers. If a write is attempted, hardware lock error is set in raw interrupt
* register. Once command is sent and a response is received from SD_MMC_CEATA cards,
* Command Done bit is set in the raw interrupt Register.
*/
uint32_t start_cmd:1;
uint32_t start_command:1;
};
uint32_t val;
} sdhost_cmd_reg_t;
@@ -573,7 +600,22 @@ typedef union {
* Bit 1 (RE): Response error;
* Bit 0 (CD): Card detect.
*/
uint32_t int_status_raw:16;
uint32_t cd:1;
uint32_t re:1;
uint32_t cmd_done:1;
uint32_t dto:1;
uint32_t txdr:1;
uint32_t rxdr:1;
uint32_t rcrc:1;
uint32_t dcrc:1;
uint32_t rto:1;
uint32_t drto:1;
uint32_t hto:1;
uint32_t frun:1;
uint32_t hle:1;
uint32_t sbi_bci:1;
uint32_t acd:1;
uint32_t ebe:1;
/** sdio_interrupt_raw : R/W; bitpos: [17:16]; default: 0;
* Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
* card0, respectively. Setting a bit clears the corresponding interrupt bit and
@@ -809,21 +851,6 @@ typedef union {
} sdhost_usrid_reg_t;
/** Group: Version ID (scratchpad) register */
/** Type of verid register
* Version ID (scratchpad) register
*/
typedef union {
struct {
/** versionid_reg : RO; bitpos: [31:0]; default: 1412572938;
* Hardware version register. Can also be read by fireware.
*/
uint32_t versionid_reg:32;
};
uint32_t val;
} sdhost_verid_reg_t;
/** Group: Hardware feature register */
/** Type of hcon register
* Hardware feature register
@@ -881,12 +908,12 @@ typedef union {
typedef union {
struct {
uint32_t reserved_0:16;
/** ddr_reg : R/W; bitpos: [17:16]; default: 0;
/** ddr : R/W; bitpos: [17:16]; default: 0;
* DDR mode selecton,1 bit for each card.
* 0-Non-DDR mdoe.
* 1-DDR mdoe.
*/
uint32_t ddr_reg:2;
uint32_t ddr:2;
uint32_t reserved_18:14;
};
uint32_t val;
@@ -920,23 +947,23 @@ typedef union {
*/
typedef union {
struct {
/** bmod_swr : R/W; bitpos: [0]; default: 0;
/** sw_reset : R/W; bitpos: [0]; default: 0;
* Software Reset. When set, the DMA Controller resets all its internal registers. It
* is automatically cleared after one clock cycle.
*/
uint32_t bmod_swr:1;
/** bmod_fb : R/W; bitpos: [1]; default: 0;
uint32_t sw_reset:1;
/** fb : R/W; bitpos: [1]; default: 0;
* Fixed Burst. Controls whether the AHB Master interface performs fixed burst
* transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16
* during start of normal burst transfers. When reset, the AHB will use SINGLE and
* INCR burst transfer operations.
*/
uint32_t bmod_fb:1;
uint32_t fb:1;
uint32_t reserved_2:5;
/** bmod_de : R/W; bitpos: [7]; default: 0;
/** enable : R/W; bitpos: [7]; default: 0;
* IDMAC Enable. When set, the IDMAC is enabled.
*/
uint32_t bmod_de:1;
uint32_t enable:1;
/** bmod_pbl : R/W; bitpos: [10:8]; default: 0;
* Programmable Burst Length. These bits indicate the maximum number of beats to be
* performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always
@@ -1088,16 +1115,16 @@ typedef union {
*/
typedef union {
struct {
/** idinten_ti : R/W; bitpos: [0]; default: 0;
/** ti : R/W; bitpos: [0]; default: 0;
* Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
* Interrupt is enabled. When reset, Transmit Interrupt is disabled.
*/
uint32_t idinten_ti:1;
/** idinten_ri : R/W; bitpos: [1]; default: 0;
uint32_t ti:1;
/** ri : R/W; bitpos: [1]; default: 0;
* Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
* Interrupt is enabled. When reset, Receive Interrupt is disabled.
*/
uint32_t idinten_ri:1;
uint32_t ri:1;
/** idinten_fbe : R/W; bitpos: [2]; default: 0;
* Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
* Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is
@@ -1116,13 +1143,13 @@ typedef union {
*/
uint32_t idinten_ces:1;
uint32_t reserved_6:2;
/** idinten_ni : R/W; bitpos: [8]; default: 0;
/** ni : R/W; bitpos: [8]; default: 0;
* Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When
* reset, a normal interrupt is disabled. This bit enables the following bits:
* IDINTEN[0]: Transmit Interrupt;
* IDINTEN[1]: Receive Interrupt.
*/
uint32_t idinten_ni:1;
uint32_t ni:1;
/** idinten_ai : R/W; bitpos: [9]; default: 0;
* Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This
* bit enables the following bits:
@@ -1182,12 +1209,12 @@ typedef union {
* 1'b1-Card read threshold enabled.
*/
uint32_t cardrdthren_reg:1;
/** cardclrinten_reg : R/W; bitpos: [1]; default: 0;
/** busy_clr_int_en : R/W; bitpos: [1]; default: 0;
* Busy clear interrupt generation:
* 1'b0-Busy clear interrypt disabled.
* 1'b1-Busy clear interrypt enabled.
*/
uint32_t cardclrinten_reg:1;
uint32_t busy_clr_int_en:1;
/** cardwrthren_reg : R/W; bitpos: [2]; default: 0;
* Applicable when HS400 mode is enabled.
* 1'b0-Card write Threshold disabled.
@@ -1392,7 +1419,7 @@ typedef union {
} sdhost_dll_conf_reg_t;
typedef struct {
typedef struct sdmmc_dev_t {
volatile sdhost_ctrl_reg_t ctrl;
uint32_t reserved_004;
volatile sdhost_clkdiv_reg_t clkdiv;
@@ -1403,12 +1430,9 @@ typedef struct {
volatile sdhost_blksiz_reg_t blksiz;
volatile sdhost_bytcnt_reg_t bytcnt;
volatile sdhost_intmask_reg_t intmask;
volatile sdhost_cmdarg_reg_t cmdarg;
volatile uint32_t cmdarg;
volatile sdhost_cmd_reg_t cmd;
volatile sdhost_resp0_reg_t resp0;
volatile sdhost_resp1_reg_t resp1;
volatile sdhost_resp2_reg_t resp2;
volatile sdhost_resp3_reg_t resp3;
volatile uint32_t resp[4]; ///< Response from card
volatile sdhost_mintsts_reg_t mintsts;
volatile sdhost_rintsts_reg_t rintsts;
volatile sdhost_status_reg_t status;
@@ -1420,7 +1444,7 @@ typedef struct {
volatile sdhost_tbbcnt_reg_t tbbcnt;
volatile sdhost_debnce_reg_t debnce;
volatile sdhost_usrid_reg_t usrid;
volatile sdhost_verid_reg_t verid;
volatile uint32_t verid;
volatile sdhost_hcon_reg_t hcon;
volatile sdhost_uhs_reg_t uhs;
volatile sdhost_rst_n_reg_t rst_n;
@@ -1444,11 +1468,14 @@ typedef struct {
volatile sdhost_raw_ints_reg_t raw_ints;
volatile sdhost_dll_clk_conf_reg_t dll_clk_conf;
volatile sdhost_dll_conf_reg_t dll_conf;
} sdhost_dev_t;
} sdmmc_dev_t;
extern sdmmc_dev_t SDMMC;
typedef sdhost_cmd_reg_t sdmmc_hw_cmd_t;
#ifndef __cplusplus
_Static_assert(sizeof(sdhost_dev_t) == 0x810, "Invalid size of sdhost_dev_t structure");
_Static_assert(sizeof(sdmmc_dev_t) == 0x810, "Invalid size of sdmmc_dev_t structure");
#endif
#ifdef __cplusplus

24
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -78,7 +78,7 @@
#define SOC_SPIRAM_SUPPORTED 1
#define SOC_PSRAM_DMA_CAPABLE 1
// #define SOC_ULP_SUPPORTED 1 //TODO: IDF-7534
// #define SOC_SDMMC_HOST_SUPPORTED 1 //TODO: IDF-6502
#define SOC_SDMMC_HOST_SUPPORTED 1
// #define SOC_CLK_TREE_SUPPORTED 1 //TODO: IDF-7526
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: IDF-7565
#define SOC_WDT_SUPPORTED 1
@@ -343,6 +343,19 @@
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (4096)
/*-------------------------- SDMMC CAPS -----------------------------------------*/
/**
* Card detect, write protect, interrupt use GPIO Matrix on all chips.
* Slot 0 clock/cmd/data pins use IOMUX
* Slot 1 clock/cmd/data pins use GPIO Matrix
*/
#define SOC_SDMMC_USE_IOMUX 1
#define SOC_SDMMC_USE_GPIO_MATRIX 1
#define SOC_SDMMC_NUM_SLOTS 2
/* Supported host clock delay phase number */
#define SOC_SDMMC_DELAY_PHASE_NUM 4
// TODO: IDF-5353 (Copy from esp32c3, need check)
/*--------------------------- SHA CAPS ---------------------------------------*/
@@ -367,15 +380,6 @@
/*--------------------------- ECDSA CAPS ---------------------------------------*/
#define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)
#ifdef SDMMC_DEFAULT_IOMUX
#define SOC_SDMMC_USE_IOMUX 1
#else
#define SOC_SDMMC_USE_GPIO_MATRIX 1
#endif
#define SOC_SDMMC_NUM_SLOTS 2
#define SOC_SDMMC_IOMUX_FUNC 0
#define SOC_SDMMC_DMA_NEED_CACHE_WB 1
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4