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fix(gpio): esp32p4 IOs cannot keep being held in the entire deep sleep process

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This commit is contained in:
Song Ruo Jing
2024-08-05 21:00:37 +08:00
parent 1171c3c281
commit 706935f468
30 changed files with 156 additions and 25 deletions
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60
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
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@@ -878,3 +878,63 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_GPIO);
}
#endif
#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
// Pick one digital IO for each target to test is enough
static void gpio_deep_sleep_hold_test_first_stage(void)
{
printf("configure a digital pin to hold during deep sleep");
int io_num = TEST_GPIO_DEEP_SLEEP_HOLD_PIN;
TEST_ASSERT(GPIO_IS_VALID_DIGITAL_IO_PAD(io_num));
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2000000));
gpio_config_t io_conf = {
.intr_type = GPIO_INTR_DISABLE,
.mode = GPIO_MODE_INPUT_OUTPUT,
.pin_bit_mask = (1ULL << io_num),
.pull_down_en = 0,
.pull_up_en = 0,
};
TEST_ESP_OK(gpio_config(&io_conf));
TEST_ESP_OK(gpio_set_level(io_num, 0));
// Enable global persistence
TEST_ESP_OK(gpio_hold_en(io_num));
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
// On such target, digital IOs cannot be held individually in Deep-sleep
// Extra step is required, so that all digital IOs can automatically get held when entering Deep-sleep
gpio_deep_sleep_hold_en();
#endif
esp_deep_sleep_start();
}
static void gpio_deep_sleep_hold_test_second_stage(void)
{
int io_num = TEST_GPIO_DEEP_SLEEP_HOLD_PIN;
// Check reset reason is waking up from deepsleep
TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
// Pin should stay at low level after the deep sleep
TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
// Set level should not take effect since hold is still active (and the INPUT_OUTPUT mode should still be held)
TEST_ESP_OK(gpio_set_level(io_num, 1));
TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
gpio_deep_sleep_hold_dis();
#endif
TEST_ESP_OK(gpio_hold_dis(io_num));
}
/*
* Test digital IOs hold function during deep sleep.
* This test case can only check the hold state after waking up from deep sleep
* If you want to check that the digital IO hold function works properly during deep sleep,
* please use logic analyzer or oscilloscope
*/
TEST_CASE_MULTIPLE_STAGES("GPIO_deep_sleep_output_hold_test", "[gpio]",
gpio_deep_sleep_hold_test_first_stage,
gpio_deep_sleep_hold_test_second_stage)
#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP

12
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,27 +20,37 @@ extern "C" {
#define TEST_GPIO_INPUT_ONLY_PIN (34)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (4)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC224_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (5)
#elif CONFIG_IDF_TARGET_ESP32S2
#define TEST_GPIO_EXT_OUT_IO (17)
#define TEST_GPIO_EXT_IN_IO (21)
#define TEST_GPIO_INPUT_ONLY_PIN (46)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC223_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (45)
#elif CONFIG_IDF_TARGET_ESP32S3
#define TEST_GPIO_EXT_OUT_IO (17)
#define TEST_GPIO_EXT_IN_IO (21)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC208_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (45)
#elif CONFIG_IDF_TARGET_ESP32P4
#define TEST_GPIO_EXT_OUT_IO (2)
#define TEST_GPIO_EXT_IN_IO (3)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC250_IDX)
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_GPIO_EXT_OUT_IO (2)
#define TEST_GPIO_EXT_IN_IO (3)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC97_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (25)
#else
#define TEST_GPIO_EXT_OUT_IO (2)
#define TEST_GPIO_EXT_IN_IO (3)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC97_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (9)
#endif
#ifdef __cplusplus

8
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -235,10 +235,10 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
#endif //SOC_RTCIO_HOLD_SUPPORTED
#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_DEEP_SLEEP_SUPPORTED
#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
// It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
// Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12, P4: IO5, C5: IO5) these pads' default configuration is low level
// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12, C5: IO5) these pads' default configuration is low level
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5
static void rtcio_deep_sleep_hold_test_first_stage(void)
@@ -284,4 +284,4 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]",
rtcio_deep_sleep_hold_test_first_stage,
rtcio_deep_sleep_hold_test_second_stage)
#endif // SOC_DEEP_SLEEP_SUPPORTED
#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP