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feat(esp32c5mp): update hal files for esp32c5 mp

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This commit is contained in:
laokaiyao
2024-03-11 10:30:36 +08:00
parent 0bbee51829
commit 71257c6ef4
14 changed files with 612 additions and 54 deletions
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149
components/hal/esp32c5/include/hal/gpio_ll.h
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@@ -16,17 +16,28 @@
#include <stdlib.h>
#include <stdbool.h>
#include "sdkconfig.h" // TODO: IDF-9197 remove
#include "soc/soc.h"
#include "soc/gpio_periph.h"
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/lp_io_struct.h"
#include "soc/pmu_struct.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "soc/lp_io_struct.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/usb_serial_jtag_struct.h"
#include "soc/io_mux_struct.h"
#include "hal/gpio_types.h"
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#include "soc/lp_gpio_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/io_mux_struct.h"
#include "hal/gpio_types.h"
#include "hal/misc.h"
#endif
#include "hal/assert.h"
#ifdef __cplusplus
@@ -77,7 +88,12 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*/
static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_wpu = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
abort();
#endif
}
/**
@@ -89,7 +105,12 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_wpu = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
abort();
#endif
}
/**
@@ -100,7 +121,12 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_wpd = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
abort();
#endif
}
/**
@@ -117,11 +143,20 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
// Note that esp32C5 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
// which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
// TODO: read the specific efuse with efuse_ll.h
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
USB_SERIAL_JTAG.conf0.dp_pullup = 0;
}
IOMUX.gpio[gpio_num].fun_wpd = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
// SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
// }
// REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
abort();
#endif
}
/**
@@ -147,7 +182,11 @@ __attribute__((always_inline))
static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
(void)core_id;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
*status = hw->pcpu_int.procpu_int;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
abort();
#endif
}
/**
@@ -222,7 +261,12 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_ie = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -233,7 +277,12 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_ie = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -244,7 +293,12 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].filter_en = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -255,9 +309,15 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].filter_en = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief Enable GPIO hysteresis
*
@@ -285,6 +345,7 @@ static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t
IOMUX.gpio[gpio_num].hys_sel = 1;
IOMUX.gpio[gpio_num].hys_en = 0;
}
#endif
/**
* @brief Disable output mode on GPIO.
@@ -400,7 +461,12 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].fun_drv = strength;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
abort();
#endif
}
/**
@@ -412,7 +478,12 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
*strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
abort();
#endif
}
/**
@@ -477,10 +548,18 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
*/
static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Disable USB Serial JTAG if pins 25 or pins 26 needs to select an IOMUX function
if (pin_name == IO_MUX_GPIO25_REG || pin_name == IO_MUX_GPIO26_REG) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
// if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
// }
abort();
#endif
PIN_FUNC_SELECT(pin_name, func);
}
@@ -506,11 +585,20 @@ static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t
__attribute__((always_inline))
static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Disable USB Serial JTAG if pins 25 or pins 26 needs to select an IOMUX function
if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
}
IOMUX.gpio[gpio_num].mcu_sel = func;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
// if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
// CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
// }
// PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
abort();
#endif
}
/**
@@ -537,6 +625,7 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
{
switch (src) {
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
break;
@@ -546,6 +635,14 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
case SOC_MOD_CLK_PLL_F80M:
PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
break;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
case SOC_MOD_CLK_XTAL:
PCR.iomux_clk_conf.iomux_func_clk_sel = 3;
break;
case SOC_MOD_CLK_PLL_F80M:
PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
break;
#endif
default:
// Unsupported IO_MUX clock source
HAL_ASSERT(false);
@@ -597,7 +694,12 @@ static inline void gpio_ll_force_unhold_all(void)
*/
static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].slp_sel = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -609,7 +711,12 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].slp_sel = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -620,7 +727,12 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpu = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -631,7 +743,12 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpu = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -642,7 +759,12 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpd = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -653,7 +775,12 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_wpd = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -664,7 +791,12 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_ie = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -675,7 +807,12 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
*/
static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_ie = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -686,7 +823,12 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
*/
static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_oe = 0;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
/**
@@ -697,7 +839,12 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
*/
static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
IOMUX.gpio[gpio_num].mcu_oe = 1;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
abort();
#endif
}
#ifdef __cplusplus