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https://github.com/espressif/esp-idf.git
synced 2025-08-21 16:55:33 +00:00
i2s: add XTAL clock source
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@@ -14,6 +14,7 @@
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#pragma once
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#include <stdbool.h>
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#include "hal/misc.h"
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#include "hal/assert.h"
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#include "soc/i2s_periph.h"
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#include "soc/i2s_struct.h"
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#include "hal/i2s_types.h"
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@@ -23,11 +24,10 @@
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extern "C" {
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#endif
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#define I2S_LL_GET_HW(num) (&I2S0)
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#define I2S_LL_GET_HW(num) (((num) == 0)? (&I2S0) : NULL)
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#define I2S_LL_TDM_CH_MASK (0xffff)
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#define I2S_LL_PDM_BCK_FACTOR (64)
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#define I2S_LL_BASE_CLK (2*APB_CLK_FREQ)
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#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9)
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#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
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@@ -193,18 +193,40 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
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*/
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static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
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{
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hw->tx_clkm_conf.tx_clk_sel = 2;
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switch (src)
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{
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case I2S_CLK_SRC_XTAL:
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hw->tx_clkm_conf.tx_clk_sel = 0;
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break;
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case I2S_CLK_SRC_PLL_160M:
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hw->tx_clkm_conf.tx_clk_sel = 2;
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break;
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default:
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HAL_ASSERT(false && "unsupported clock source");
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break;
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}
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}
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/**
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* @brief Set RX source clock
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*
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* @param hw Peripheral I2S hardware instance address.
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* @param src I2S source clock, ESP32-C3 only support `I2S_CLK_SRC_PLL_160M`
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* @param src I2S source clock
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*/
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static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
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{
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hw->rx_clkm_conf.rx_clk_sel = 2;
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switch (src)
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{
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case I2S_CLK_SRC_XTAL:
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hw->rx_clkm_conf.rx_clk_sel = 0;
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break;
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case I2S_CLK_SRC_PLL_160M:
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hw->rx_clkm_conf.rx_clk_sel = 2;
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break;
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default:
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hw->rx_clkm_conf.rx_clk_sel = 2;
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break;
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}
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}
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/**
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