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esp_gdbstub: refactor code

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This commit is contained in:
Alexey Lapshin
2023-04-02 23:29:27 +08:00
parent 961018d882
commit 71a19d238c
27 changed files with 277 additions and 904 deletions
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81
components/esp_gdbstub/src/port/riscv/gdbstub_riscv.c Normal file
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/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "esp_gdbstub.h"
#include "esp_gdbstub_common.h"
#include "sdkconfig.h"
static inline void init_regfile(esp_gdbstub_gdb_regfile_t *dst)
{
memset(dst, 0, sizeof(*dst));
}
void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_gdb_regfile_t *dst)
{
init_regfile(dst);
dst->pc = frame->mepc;
// We omit register x0 here since it's the zero register and always hard-wired to 0.
// See The RISC-V Instruction Set Manual Volume I: Unprivileged ISA Document Version 20191213 for more details.
memcpy(&(dst->x[1]), &frame->ra, sizeof(uint32_t) * 31);
}
#ifdef CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
/* Represents FreeRTOS TCB structure */
typedef struct {
uint8_t *top_of_stack;
/* Other members aren't needed */
} dummy_tcb_t;
void esp_gdbstub_tcb_to_regfile(TaskHandle_t tcb, esp_gdbstub_gdb_regfile_t *dst)
{
const dummy_tcb_t *dummy_tcb = (const dummy_tcb_t *) tcb;
const RvExcFrame *frame = (RvExcFrame *) dummy_tcb->top_of_stack;
esp_gdbstub_frame_to_regfile(frame, dst);
}
#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
int esp_gdbstub_get_signal(const esp_gdbstub_frame_t *frame)
{
return 5; // SIGTRAP, see IDF-2490
}
void _xt_gdbstub_int(void *frame)
{
}
void esp_gdbstub_init_dports()
{
}
void esp_gdbstub_stall_other_cpus_start()
{
}
void esp_gdbstub_stall_other_cpus_end()
{
}
void esp_gdbstub_clear_step()
{
}
void esp_gdbstub_do_step()
{
}
void esp_gdbstub_trigger_cpu(void)
{
}
void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t value)
{
}

36
components/esp_gdbstub/src/port/riscv/include/esp_gdbstub_arch.h Normal file
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/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "riscv/rvruntime-frames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef RvExcFrame esp_gdbstub_frame_t;
/* GDB regfile structure, configuration dependent */
typedef struct {
uint32_t x[32];
uint32_t pc;
} esp_gdbstub_gdb_regfile_t;
// Amount of HW breakpoints used in GDB
#ifndef GDB_BP_SIZE
#define GDB_BP_SIZE 2
#endif // GDB_BP_SIZE
// Amount of HW watchpoints used in GDB
#ifndef GDB_WP_SIZE
#define GDB_WP_SIZE 2
#endif // GDB_WP_SIZE
#ifdef __cplusplus
}
#endif

41
components/esp_gdbstub/src/port/riscv/include/esp_gdbstub_memory_regions.h Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_gdbstub_memory_regions_common.h"
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline bool __is_valid_memory_region(intptr_t addr)
{
return (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH) ||
(addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH) ||
(addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH) ||
(addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH) ||
(addr >= SOC_IROM_MASK_LOW && addr < SOC_IROM_MASK_HIGH) ||
(addr >= SOC_DROM_MASK_LOW && addr < SOC_DROM_MASK_HIGH) ||
#if defined(SOC_RTC_IRAM_LOW) && defined(SOC_RTC_IRAM_HIGH)
(addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH) ||
/* RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them */
#endif
(addr >= SOC_PERIPHERAL_LOW && addr < SOC_PERIPHERAL_HIGH) ||
(addr >= SOC_DEBUG_LOW && addr < SOC_DEBUG_HIGH);
}
static inline bool is_valid_memory_region(intptr_t addr)
{
/* We shouldn't read transport registers since it will disturb the debugging. */
return (!is_transport_memory_region(addr)) && __is_valid_memory_region(addr);
}
#ifdef __cplusplus
}
#endif

58
components/esp_gdbstub/src/port/xtensa/gdbstub-entry.S Normal file
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "freertos/xtensa_rtos.h"
.section .iram1, "ax"
.global gdbstub_handle_uart_int
.global _xt_gdbstub_int
.align 4
_xt_gdbstub_int:
/* Allocate exception frame and save minimal context. */
mov a0, sp
addi sp, sp, -XT_STK_FRMSZ
s32i a0, sp, XT_STK_EXIT
s32i a0, sp, XT_STK_A0
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -12 /* for debug backtrace */
#endif
rsr a0, PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -16 /* for debug backtrace */
#endif
s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
/* Save exc cause and vaddr into exception frame */
rsr a0, EXCCAUSE
s32i a0, sp, XT_STK_EXCCAUSE
rsr a0, EXCVADDR
s32i a0, sp, XT_STK_EXCVADDR
/* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
/* Save context pointer as input parameter */
rsr a6, excsave1
rsr a3, EPS
s32i a3, sp, XT_STK_PS // store PS to the ps place
movi a3, gdbstub_handle_uart_int
callx0 a3
l32i a0, sp, XT_STK_EXIT
addi sp, sp, XT_STK_FRMSZ
ret

219
components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c Normal file
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/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "esp_gdbstub_common.h"
#include "soc/soc_memory_layout.h"
#include "xtensa/config/specreg.h"
#include "sdkconfig.h"
#include "esp_cpu.h"
#include "esp_ipc_isr.h"
#include "esp_private/crosscore_int.h"
#if !XCHAL_HAVE_WINDOWED
#warning "gdbstub_xtensa: revisit the implementation for Call0 ABI"
#endif
extern int _invalid_pc_placeholder;
static inline void init_regfile(esp_gdbstub_gdb_regfile_t *dst)
{
memset(dst, 0, sizeof(*dst));
}
static void update_regfile_common(esp_gdbstub_gdb_regfile_t *dst)
{
if (dst->a[0] & 0x8000000U) {
dst->a[0] = (uint32_t)esp_cpu_pc_to_addr(dst->a[0]);
}
if (!esp_stack_ptr_is_sane(dst->a[1])) {
dst->a[1] = 0xDEADBEEF;
}
dst->windowbase = 0;
dst->windowstart = 0x1;
RSR(CONFIGID0, dst->configid0);
RSR(CONFIGID1, dst->configid1);
}
void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_gdb_regfile_t *dst)
{
init_regfile(dst);
const uint32_t *a_regs = (const uint32_t *) &frame->a0;
if (!(esp_ptr_executable(esp_cpu_pc_to_addr(frame->pc)) && (frame->pc & 0xC0000000U))) {
/* Xtensa ABI sets the 2 MSBs of the PC according to the windowed call size
* Incase the PC is invalid, GDB will fail to translate addresses to function names
* Hence replacing the PC to a placeholder address in case of invalid PC
*/
dst->pc = (uint32_t)&_invalid_pc_placeholder;
} else {
dst->pc = (uint32_t)esp_cpu_pc_to_addr(frame->pc);
}
for (int i = 0; i < 16; i++) {
dst->a[i] = a_regs[i];
}
for (int i = 16; i < 64; i++) {
dst->a[i] = 0xDEADBEEF;
}
#if XCHAL_HAVE_LOOPS
dst->lbeg = frame->lbeg;
dst->lend = frame->lend;
dst->lcount = frame->lcount;
#endif
dst->ps = (frame->ps & PS_UM) ? (frame->ps & ~PS_EXCM) : frame->ps;
dst->sar = frame->sar;
update_regfile_common(dst);
}
#ifdef CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
static void solicited_frame_to_regfile(const XtSolFrame *frame, esp_gdbstub_gdb_regfile_t *dst)
{
init_regfile(dst);
const uint32_t *a_regs = (const uint32_t *) &frame->a0;
if (!(esp_ptr_executable(esp_cpu_pc_to_addr(frame->pc)) && (frame->pc & 0xC0000000U))) {
dst->pc = (uint32_t)&_invalid_pc_placeholder;
} else {
dst->pc = (uint32_t)esp_cpu_pc_to_addr(frame->pc);
}
/* only 4 registers saved in the solicited frame */
for (int i = 0; i < 4; i++) {
dst->a[i] = a_regs[i];
}
for (int i = 4; i < 64; i++) {
dst->a[i] = 0xDEADBEEF;
}
dst->ps = (frame->ps & PS_UM) ? (frame->ps & ~PS_EXCM) : frame->ps;
update_regfile_common(dst);
}
/* Represents FreeRTOS TCB structure */
typedef struct {
uint8_t *top_of_stack;
/* Other members aren't needed */
} dummy_tcb_t;
void esp_gdbstub_tcb_to_regfile(TaskHandle_t tcb, esp_gdbstub_gdb_regfile_t *dst)
{
const dummy_tcb_t *dummy_tcb = (const dummy_tcb_t *) tcb;
const XtExcFrame *frame = (XtExcFrame *) dummy_tcb->top_of_stack;
if (frame->exit != 0) {
esp_gdbstub_frame_to_regfile(frame, dst);
} else {
const XtSolFrame *taskFrame = (const XtSolFrame *) dummy_tcb->top_of_stack;
solicited_frame_to_regfile(taskFrame, dst);
}
}
#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS
int esp_gdbstub_get_signal(const esp_gdbstub_frame_t *frame)
{
const char exccause_to_signal[] = {4, 31, 11, 11, 2, 6, 8, 0, 6, 7, 0, 0, 7, 7, 7, 7};
if (frame->exccause >= sizeof(exccause_to_signal)) {
return 11;
}
return (int) exccause_to_signal[frame->exccause];
}
/** @brief Init dport for GDB
* Init dport for iterprocessor communications
* */
void esp_gdbstub_init_dports(void)
{
}
#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
static bool stall_started = false;
#endif
/** @brief GDB stall other CPU
* GDB stall other CPU
* */
void esp_gdbstub_stall_other_cpus_start()
{
#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
if (stall_started == false) {
esp_ipc_isr_stall_other_cpu();
stall_started = true;
}
#endif
}
/** @brief GDB end stall other CPU
* GDB end stall other CPU
* */
void esp_gdbstub_stall_other_cpus_end()
{
#if CONFIG_IDF_TARGET_ARCH_XTENSA && (!CONFIG_FREERTOS_UNICORE) && CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
if (stall_started == true) {
esp_ipc_isr_release_other_cpu();
stall_started = false;
}
#endif
}
/** @brief GDB clear step
* GDB clear step registers
* */
void esp_gdbstub_clear_step(void)
{
WSR(ICOUNT, 0);
WSR(ICOUNTLEVEL, 0);
}
/** @brief GDB do step
* GDB do one step
* */
void esp_gdbstub_do_step(void)
{
// We have gdbstub uart interrupt, and if we will call step, with ICOUNTLEVEL=2 or higher, from uart interrupt, the
// application will hang because it will try to step uart interrupt. That's why we have to set ICOUNTLEVEL=1
// If we will stop by the breakpoint inside interrupt, we will handle this interrupt with ICOUNTLEVEL=ps.intlevel+1
uint32_t level = s_scratch.regfile.ps;
level &= 0x7;
level += 1;
WSR(ICOUNTLEVEL, level);
WSR(ICOUNT, -2);
}
/** @brief GDB trigger other CPU
* GDB trigger other CPU
* */
void esp_gdbstub_trigger_cpu(void)
{
#if !CONFIG_FREERTOS_UNICORE
if (0 == esp_cpu_get_core_id()) {
esp_crosscore_int_send_gdb_call(1);
} else {
esp_crosscore_int_send_gdb_call(0);
}
#endif
}
/** @brief GDB set register in frame
* Set register in frame with address to value
*
* */
void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, uint32_t value)
{
switch (reg_index) {
case 0:
frame->pc = value;
break;
default:
(&frame->a0)[reg_index - 1] = value;
break;
}
}

101
components/esp_gdbstub/src/port/xtensa/include/esp_gdbstub_arch.h Normal file
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/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "freertos/xtensa_context.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#define GDBSTUB_EXTRA_TIE_SIZE 0
#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
#define GDBSTUB_EXTRA_TIE_SIZE 1
#else
#error "Unknown Xtensa chip"
#endif
#ifdef __cplusplus
extern "C" {
#endif
typedef XtExcFrame esp_gdbstub_frame_t;
/* GDB regfile structure, configuration dependent */
typedef struct {
uint32_t pc;
uint32_t a[XCHAL_NUM_AREGS];
#if XCHAL_HAVE_LOOPS
uint32_t lbeg;
uint32_t lend;
uint32_t lcount;
#endif
uint32_t sar;
#if XCHAL_HAVE_WINDOWED
uint32_t windowbase;
uint32_t windowstart;
#endif
uint32_t configid0;
uint32_t configid1;
uint32_t ps;
#if XCHAL_HAVE_THREADPTR
uint32_t threadptr;
#endif
#if XCHAL_HAVE_BOOLEANS
uint32_t br;
#endif
#if XCHAL_HAVE_S32C1I
uint32_t scompare1;
#endif
#if XCHAL_HAVE_MAC16
uint32_t acclo;
uint32_t acchi;
uint32_t m0;
uint32_t m1;
uint32_t m2;
uint32_t m3;
#endif
#if XCHAL_HAVE_DFP_ACCEL
uint32_t expstate;
uint32_t f64r_lo;
uint32_t f64r_hi;
uint32_t f64s;
#endif
#if XCHAL_HAVE_FP
uint32_t f[16];
uint32_t fcr;
uint32_t fsr;
#endif
#if GDBSTUB_EXTRA_TIE_SIZE > 0
uint32_t tie[GDBSTUB_EXTRA_TIE_SIZE];
#endif
} esp_gdbstub_gdb_regfile_t;
// Amount of HW breakpoints used in GDB
#ifndef GDB_BP_SIZE
#define GDB_BP_SIZE 2
#endif // GDB_BP_SIZE
// Amount of HW watchpoints used in GDB
#ifndef GDB_WP_SIZE
#define GDB_WP_SIZE 2
#endif // GDB_WP_SIZE
#ifdef __cplusplus
}
#endif

25
components/esp_gdbstub/src/port/xtensa/include/esp_gdbstub_memory_regions.h Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_gdbstub_memory_regions_common.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline bool is_valid_memory_region(intptr_t addr)
{
/* We shouldn't read transport registers since it will disturb the debugging. */
return (!is_transport_memory_region(addr)) &&
addr >= 0x20000000 && addr < 0x80000000;
}
#ifdef __cplusplus
}
#endif

64
components/esp_gdbstub/src/port/xtensa/xt_debugexception.S Normal file
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/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/coreasm.h>
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include "freertos/xtensa_context.h"
.section .iram1,"ax"
.global _xt_panic_gdbstub
.type _xt_panic_gdbstub,@function
.align 4
.literal_position
.align 4
_xt_panic_gdbstub:
/* Allocate exception frame and save minimal context. */
addi sp, sp, -XT_STK_FRMSZ
s32i a0, sp, XT_STK_EXIT
s32i a0, sp, XT_STK_A0
rsr a0, PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
call0 _xt_context_save /* Save full context*/
addi a7, sp, XT_STK_FRMSZ
s32i a7, sp, XT_STK_A1
s32i a12, sp, XT_STK_A12
s32i a13, sp, XT_STK_A13
/* Save exc cause and vaddr into exception frame */
rsr a0, EXCCAUSE
s32i a0, sp, XT_STK_EXCCAUSE
rsr a0, EXCVADDR
s32i a0, sp, XT_STK_EXCVADDR
/* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
wsr a0, PS
//Call gdbstub handler
rsr a0,(EPC + XCHAL_DEBUGLEVEL)
s32i a0, sp, XT_STK_PC
mov a6, sp
rsr a9, EPS_6
s32i a9, sp, XT_STK_PS // store PS to the ps place
movi a11, gdbstub_handle_debug_int
callx4 a11 /* Call interrupt handler */
l32i a0, sp, XT_STK_PC
wsr a0,(EPC + XCHAL_DEBUGLEVEL)
call0 _xt_context_restore /* Restore full context*/
l32i a12, sp, XT_STK_A12
l32i a13, sp, XT_STK_A13
l32i a0, sp, XT_STK_EXIT /* Restore return point*/
addi sp, sp, XT_STK_FRMSZ /* Restore SP*/
rfi 6 // Return from high-level interrupt