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Merge branch 'feature/efuse_update_for_esp32h2_eco5_v5.4' into 'release/v5.4'

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feat(efuse): Adds efuses for esp32h2 eco5 (v5.4)

See merge request espressif/esp-idf!36238
This commit is contained in:
Jiang Jiang Jian
2025-01-17 11:39:31 +08:00
parent 054a0be454 a98c20d4e0
commit 74896d4187
13 changed files with 255 additions and 70 deletions
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4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@@ -3,6 +3,10 @@
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_CAPS_ECO_VER_MAX
int
default 102
config SOC_ADC_SUPPORTED
bool
default y

19
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -16,7 +16,24 @@
#pragma once
#ifdef __has_include
# if __has_include("sdkconfig.h")
# include "sdkconfig.h"
# define SOC_CAPS_ECO_VER CONFIG_ESP32H2_REV_MIN_FULL
# endif
#endif
#if !defined(SOC_CAPS_ECO_VER)
#define SOC_CAPS_ECO_VER SOC_CAPS_ECO_VER_MAX
#endif
#ifndef SOC_CAPS_ECO_VER
#warning ECO version not determined. Some ECO related caps will not be available.
#warning Define SOC_CAPS_ECO_VER before including this header.
#endif
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_CAPS_ECO_VER_MAX 102
#define SOC_ADC_SUPPORTED 1
#define SOC_ANA_CMPR_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
@@ -474,7 +491,9 @@
#define SOC_EFUSE_SOFT_DIS_JTAG 1
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block
#if SOC_CAPS_ECO_VER < 102
#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA
#endif
#define SOC_EFUSE_ECDSA_KEY 1
/*-------------------------- Secure Boot CAPS----------------------------*/

71
components/soc/esp32h2/register/soc/efuse_reg.h
View File

@@ -289,27 +289,30 @@ extern "C" {
#define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
#define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U
#define EFUSE_VDD_SPI_AS_GPIO_S 26
/** EFUSE_RPT4_RESERVED0_2 : RO; bitpos: [28:27]; default: 0;
* Reserved.
/** EFUSE_ECDSA_CURVE_MODE : R; bitpos: [28:27]; default: 0;
* Configures the curve of ECDSA calculation: 0: only enable P256. 1: only enable
* P192. 2: both enable P256 and P192. 3: only enable P256
*/
#define EFUSE_RPT4_RESERVED0_2 0x00000003U
#define EFUSE_RPT4_RESERVED0_2_M (EFUSE_RPT4_RESERVED0_2_V << EFUSE_RPT4_RESERVED0_2_S)
#define EFUSE_RPT4_RESERVED0_2_V 0x00000003U
#define EFUSE_RPT4_RESERVED0_2_S 27
/** EFUSE_RPT4_RESERVED0_1 : RO; bitpos: [29]; default: 0;
* Reserved.
#define EFUSE_ECDSA_CURVE_MODE 0x00000003U
#define EFUSE_ECDSA_CURVE_MODE_M (EFUSE_ECDSA_CURVE_MODE_V << EFUSE_ECDSA_CURVE_MODE_S)
#define EFUSE_ECDSA_CURVE_MODE_V 0x00000003U
#define EFUSE_ECDSA_CURVE_MODE_S 27
/** EFUSE_ECC_FORCE_CONST_TIME : R; bitpos: [29]; default: 0;
* Set this bit to permanently turn on ECC const-time mode
*/
#define EFUSE_RPT4_RESERVED0_1 (BIT(29))
#define EFUSE_RPT4_RESERVED0_1_M (EFUSE_RPT4_RESERVED0_1_V << EFUSE_RPT4_RESERVED0_1_S)
#define EFUSE_RPT4_RESERVED0_1_V 0x00000001U
#define EFUSE_RPT4_RESERVED0_1_S 29
/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0;
* Reserved.
#define EFUSE_ECC_FORCE_CONST_TIME (BIT(29))
#define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S)
#define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U
#define EFUSE_ECC_FORCE_CONST_TIME_S 29
/** EFUSE_XTS_DPA_PSEUDO_LEVEL : R; bitpos: [31:30]; default: 0;
* Set this bit to control the xts pseudo-round anti-dpa attack function: 0:
* controlled by register. 1-3: the higher the value is, the more pseudo-rounds are
* inserted to the xts-aes calculation
*/
#define EFUSE_RPT4_RESERVED0_0 0x00000003U
#define EFUSE_RPT4_RESERVED0_0_M (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S)
#define EFUSE_RPT4_RESERVED0_0_V 0x00000003U
#define EFUSE_RPT4_RESERVED0_0_S 30
#define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U
#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S)
#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U
#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 30
/** EFUSE_RD_REPEAT_DATA1_REG register
* BLOCK0 data register 2.
@@ -416,14 +419,13 @@ extern "C" {
#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U
#define EFUSE_SEC_DPA_LEVEL_S 16
/** EFUSE_ECDSA_FORCE_USE_HARDWARE_K : RO; bitpos: [18]; default: 1;
* Represents whether hardware random number k is forced used in ESDCA. 1: force used.
* 0: not force used.
/** EFUSE_RESERVE_0_114 : RO; bitpos: [18]; default: 1;
* Reserved
*/
#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K (BIT(18))
#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_M (EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V << EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S)
#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V 0x00000001U
#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S 18
#define EFUSE_RESERVE_0_114 (BIT(18))
#define EFUSE_RESERVE_0_114_M (EFUSE_RESERVE_0_114_V << EFUSE_RESERVE_0_114_S)
#define EFUSE_RESERVE_0_114_V 0x00000001U
#define EFUSE_RESERVE_0_114_S 18
/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
* Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
*/
@@ -446,13 +448,20 @@ extern "C" {
#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U
#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21
/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0;
* Reserved.
/** EFUSE_POWERGLITCH_EN1 : R; bitpos: [26:22]; default: 0;
* Set these bits to enable power glitch function when chip power on
*/
#define EFUSE_RPT4_RESERVED2_0 0x0000003FU
#define EFUSE_RPT4_RESERVED2_0_M (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S)
#define EFUSE_RPT4_RESERVED2_0_V 0x0000003FU
#define EFUSE_RPT4_RESERVED2_0_S 22
#define EFUSE_POWERGLITCH_EN1 0x0000001FU
#define EFUSE_POWERGLITCH_EN1_M (EFUSE_POWERGLITCH_EN1_V << EFUSE_POWERGLITCH_EN1_S)
#define EFUSE_POWERGLITCH_EN1_V 0x0000001FU
#define EFUSE_POWERGLITCH_EN1_S 22
/** EFUSE_RESERVED_0_123 : R; bitpos: [27]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_0_123 (BIT(27))
#define EFUSE_RESERVED_0_123_M (EFUSE_RESERVED_0_123_V << EFUSE_RESERVED_0_123_S)
#define EFUSE_RESERVED_0_123_V 0x00000001U
#define EFUSE_RESERVED_0_123_S 27
/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
* Represents the flash waiting time after power-up, in unit of ms. When the value
* less than 15, the waiting time is the programmed value. Otherwise, the waiting time

38
components/soc/esp32h2/register/soc/efuse_struct.h
View File

@@ -252,18 +252,21 @@ typedef union {
* functioned.
*/
uint32_t vdd_spi_as_gpio:1;
/** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0;
* Reserved.
/** ecdsa_curve_mode : R; bitpos: [28:27]; default: 0;
* Configures the curve of ECDSA calculation: 0: only enable P256. 1: only enable
* P192. 2: both enable P256 and P192. 3: only enable P256
*/
uint32_t rpt4_reserved0_2:2;
/** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0;
* Reserved.
uint32_t ecdsa_curve_mode:2;
/** ecc_force_const_time : R; bitpos: [29]; default: 0;
* Set this bit to permanently turn on ECC const-time mode
*/
uint32_t rpt4_reserved0_1:1;
/** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0;
* Reserved.
uint32_t ecc_force_const_time:1;
/** xts_dpa_pseudo_level : R; bitpos: [31:30]; default: 0;
* Set this bit to control the xts pseudo-round anti-dpa attack function: 0:
* controlled by register. 1-3: the higher the value is, the more pseudo-rounds are
* inserted to the xts-aes calculation
*/
uint32_t rpt4_reserved0_0:2;
uint32_t xts_dpa_pseudo_level:2;
};
uint32_t val;
} efuse_rd_repeat_data0_reg_t;
@@ -339,11 +342,10 @@ typedef union {
* Represents the spa secure level by configuring the clock random divide mode.
*/
uint32_t sec_dpa_level:2;
/** ecdsa_force_use_hardware_k : RO; bitpos: [18]; default: 1;
* Represents whether hardware random number k is forced used in ESDCA. 1: force used.
* 0: not force used.
/** reserve_0_114 : RO; bitpos: [18]; default: 1;
* Reserved
*/
uint32_t ecdsa_force_use_hardware_k:1;
uint32_t reserve_0_114:1;
/** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
* Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
*/
@@ -357,10 +359,14 @@ typedef union {
* enabled. 0: disabled.
*/
uint32_t secure_boot_aggressive_revoke:1;
/** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0;
* Reserved.
/** powerglitch_en1 : R; bitpos: [26:22]; default: 0;
* Set these bits to enable power glitch function when chip power on
*/
uint32_t rpt4_reserved2_0:6;
uint32_t powerglitch_en1:5;
/** reserved_0_123 : R; bitpos: [27]; default: 0;
* reserved
*/
uint32_t reserved_0_123:1;
/** flash_tpuw : RO; bitpos: [31:28]; default: 0;
* Represents the flash waiting time after power-up, in unit of ms. When the value
* less than 15, the waiting time is the programmed value. Otherwise, the waiting time