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Merge branch 'feature/efuse_update_for_esp32h2_eco5_v5.4' into 'release/v5.4'

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feat(efuse): Adds efuses for esp32h2 eco5 (v5.4)

See merge request espressif/esp-idf!36238
This commit is contained in:
Jiang Jiang Jian
2025-01-17 11:39:31 +08:00
parent 054a0be454 a98c20d4e0
commit 74896d4187
13 changed files with 255 additions and 70 deletions
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4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@@ -3,6 +3,10 @@
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_CAPS_ECO_VER_MAX
int
default 102
config SOC_ADC_SUPPORTED
bool
default y

19
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -16,7 +16,24 @@
#pragma once
#ifdef __has_include
# if __has_include("sdkconfig.h")
# include "sdkconfig.h"
# define SOC_CAPS_ECO_VER CONFIG_ESP32H2_REV_MIN_FULL
# endif
#endif
#if !defined(SOC_CAPS_ECO_VER)
#define SOC_CAPS_ECO_VER SOC_CAPS_ECO_VER_MAX
#endif
#ifndef SOC_CAPS_ECO_VER
#warning ECO version not determined. Some ECO related caps will not be available.
#warning Define SOC_CAPS_ECO_VER before including this header.
#endif
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_CAPS_ECO_VER_MAX 102
#define SOC_ADC_SUPPORTED 1
#define SOC_ANA_CMPR_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
@@ -474,7 +491,9 @@
#define SOC_EFUSE_SOFT_DIS_JTAG 1
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block
#if SOC_CAPS_ECO_VER < 102
#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA
#endif
#define SOC_EFUSE_ECDSA_KEY 1
/*-------------------------- Secure Boot CAPS----------------------------*/