alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-19 07:55:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat(clk): Add 120M pll clock support

Browse Source
This commit is contained in:
C.S.M
2025-07-08 18:59:31 +08:00
parent 4e7bfc3217
commit 752c9fc805
4 changed files with 24 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
components/hal/esp32p4/include/hal/clk_gate_ll.h
View File

@@ -76,6 +76,21 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_160m_clk_en(bool enable)
_clk_gate_ll_ref_160m_clk_en(__VA_ARGS__); \
} while(0)
/**
* Enable or disable the clock gate for ref_120m.
* @param enable Enable / disable
*/
FORCE_INLINE_ATTR void _clk_gate_ll_ref_120m_clk_en(bool enable)
{
HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_120m_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define clk_gate_ll_ref_120m_clk_en(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_clk_gate_ll_ref_120m_clk_en(__VA_ARGS__); \
} while(0)
/**
* Enable or disable the clock gate for ref_20m.
* @param enable Enable / disable

1
components/hal/esp32p4/include/hal/clk_tree_ll.h
View File

@@ -37,6 +37,7 @@ extern "C" {
#define CLK_LL_PLL_8M_FREQ_MHZ (8)
#define CLK_LL_PLL_80M_FREQ_MHZ (80)
#define CLK_LL_PLL_120M_FREQ_MHZ (120)
#define CLK_LL_PLL_160M_FREQ_MHZ (160)
#define CLK_LL_PLL_240M_FREQ_MHZ (240)
#define CLK_LL_PLL_SDIO_FREQ_MHZ (200)