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feat(clk): Add 120M pll clock support

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C.S.M
2025-07-08 18:59:31 +08:00
parent 4e7bfc3217
commit 752c9fc805
4 changed files with 24 additions and 0 deletions
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2
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -163,6 +163,7 @@ typedef enum {
SOC_MOD_CLK_PLL_F50M, /*!< PLL_F50M_CLK is derived from MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz */
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from SPLL (clock gating + default divider 6), its default frequency is 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from SPLL (clock gating + default divider 3), its default frequency is 160MHz */
SOC_MOD_CLK_PLL_F120M, /*!< PLL_F120M_CLK is derived from SPLL (clock gating + default divider 4), its default frequency is 120MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from SPLL (clock gating + default divider 2), its default frequency is 240MHz */
SOC_MOD_CLK_CPLL, /*!< CPLL is from 40MHz XTAL oscillator frequency multipliers */
SOC_MOD_CLK_SPLL, /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, its default frequency is 480MHz */
@@ -756,6 +757,7 @@ typedef enum {
typedef enum {
I3C_MASTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
I3C_MASTER_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M,
I3C_MASTER_CLK_SRC_PLL_F120M = SOC_MOD_CLK_PLL_F120M,
I3C_MASTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
} soc_periph_i3c_master_clk_src_t;