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rom, spi_flash: add a patch for esp_flash_erase_region for C3, S3, H2
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@@ -23,6 +23,7 @@
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#include "sdkconfig.h"
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#include "esp_flash_internal.h"
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#include "spi_flash_defs.h"
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#include "esp_rom_caps.h"
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp_crypto_lock.h" // for locking flash encryption peripheral
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#endif //CONFIG_IDF_TARGET_ESP32S2
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@@ -545,6 +546,28 @@ esp_err_t IRAM_ATTR esp_flash_erase_region(esp_flash_t *chip, uint32_t start, ui
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return rom_spiflash_api_funcs->flash_end_flush_cache(chip, err, bus_acquired, start, len);
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}
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#endif // !CONFIG_SPI_FLASH_ROM_IMPL
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#if defined(CONFIG_SPI_FLASH_ROM_IMPL) && ESP_ROM_HAS_ERASE_0_REGION_BUG
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/* ROM esp_flash_erase_region implementation doesn't handle 0 erase size correctly.
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* Check the size and call ROM function instead of overriding it completely.
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* The behavior is slightly different from esp_flash_erase_region above, thought:
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* here the check for 0 size is done first, but in esp_flash_erase_region the check is
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* done after the other arguments are checked.
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*/
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extern esp_err_t rom_esp_flash_erase_region(esp_flash_t *chip, uint32_t start, uint32_t len);
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esp_err_t IRAM_ATTR esp_flash_erase_region(esp_flash_t *chip, uint32_t start, uint32_t len)
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{
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if (len == 0) {
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return ESP_OK;
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}
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return rom_esp_flash_erase_region(chip, start, len);
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}
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#endif // defined(CONFIG_SPI_FLASH_ROM_IMPL) && ESP_ROM_HAS_ERASE_0_REGION_BUG
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#ifndef CONFIG_SPI_FLASH_ROM_IMPL
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esp_err_t IRAM_ATTR esp_flash_get_chip_write_protect(esp_flash_t *chip, bool *out_write_protected)
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{
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esp_err_t err = rom_spiflash_api_funcs->chip_check(&chip);
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