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https://github.com/espressif/esp-idf.git
synced 2025-10-27 03:55:01 +00:00
global: fix sign-compare warnings
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@@ -116,7 +116,7 @@ static inline void cpu_ll_set_watchpoint(int id,
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//We support watching 2^n byte values, from 1 to 64. Calculate the mask for that.
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for (int x = 0; x < 7; x++) {
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if (size == (size_t)(1 << x)) {
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if (size == (size_t)(1U << x)) {
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break;
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}
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dbreakc <<= 1;
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@@ -122,7 +122,7 @@ static inline void sha_ll_fill_text_block(const void *input_text, size_t block_w
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uint32_t *data_words = NULL;
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reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE);
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data_words = (uint32_t *)input_text;
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for (int i = 0; i < block_word_len; i++) {
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for (size_t i = 0; i < block_word_len; i++) {
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reg_addr_buf[i] = __builtin_bswap32(data_words[i]);
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}
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}
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@@ -141,7 +141,7 @@ static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state,
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if (sha_type == SHA2_384 || sha_type == SHA2_512) {
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/* for these ciphers using 64-bit states, swap each pair of words */
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DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU.
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for (int i = 0; i < digest_word_len; i += 2) {
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for (size_t i = 0; i < digest_word_len; i += 2) {
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digest_state_words[i + 1] = DPORT_SEQUENCE_REG_READ((uint32_t)®_addr_buf[i]);
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digest_state_words[i] = DPORT_SEQUENCE_REG_READ((uint32_t)®_addr_buf[i + 1]);
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}
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@@ -147,7 +147,7 @@ static inline void spi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, ui
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} else {
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// Otherwise, slow(er) path copies word by word
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int copy_len = read_len;
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for (int i = 0; i < (read_len + 3) / 4; i++) {
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for (size_t i = 0; i < (read_len + 3) / 4; i++) {
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int word_len = MIN(sizeof(uint32_t), copy_len);
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uint32_t word = dev->data_buf[i];
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memcpy(buffer, &word, word_len);
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@@ -268,7 +268,7 @@ static inline void spi_ll_dma_set_rx_eof_generation(spi_dev_t *hw, bool enable)
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*/
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static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen)
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{
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for (int x = 0; x < bitlen; x += 32) {
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for (size_t x = 0; x < bitlen; x += 32) {
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//Use memcpy to get around alignment issues for txdata
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uint32_t word;
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memcpy(&word, &buffer_to_send[x / 8], 4);
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@@ -285,7 +285,7 @@ static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_s
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*/
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static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen)
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{
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for (int x = 0; x < bitlen; x += 32) {
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for (size_t x = 0; x < bitlen; x += 32) {
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//Do a memcpy to get around possible alignment issues in rx_buffer
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uint32_t word = hw->data_buf[x / 32];
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int len = bitlen - x;
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@@ -207,7 +207,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd
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{
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//Get the UART APB fifo addr. Read fifo, we use APB address
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uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2);
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for(int i = 0; i < rd_len; i++) {
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for(uint32_t i = 0; i < rd_len; i++) {
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buf[i] = READ_PERI_REG(fifo_addr);
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#ifdef CONFIG_COMPILER_OPTIMIZATION_PERF
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__asm__ __volatile__("nop");
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@@ -228,7 +228,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint
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{
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//Get the UART AHB fifo addr, Write fifo, we use AHB address
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uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_AHB_REG(0) : (hw == &UART1) ? UART_FIFO_AHB_REG(1) : UART_FIFO_AHB_REG(2);
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for(int i = 0; i < wr_len; i++) {
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for(uint32_t i = 0; i < wr_len; i++) {
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WRITE_PERI_REG(fifo_addr, buf[i]);
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}
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}
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