alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-22 01:02:57 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/esp32c5_eco1_wifi_ps' into 'master'

Browse Source 
fix some wifi power save issues and optimize phy sleep for esp32c5 eco1 and beta5

Closes PM-306, PM-319, PM-320, PM-296, PM-308, PM-311, PM-310, PM-309, PM-295, PM-274, PM-271, IDFCI-2604, and IDFCI-2605

See merge request espressif/esp-idf!35093
This commit is contained in:
Jiang Jiang Jian
2025-01-21 15:46:04 +08:00
parent d75ca966c3 84ecd39c81
commit 767545693a
24 changed files with 294 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
components/hal/esp32c5/include/hal/clk_tree_ll.h
View File

@@ -9,16 +9,19 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/pcr_reg.h"
#include "soc/pcr_struct.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/pmu_reg.h"
#include "soc/pmu_struct.h"
#include "soc/chip_revision.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_bbpll.h"
#include "hal/assert.h"
#include "hal/log.h"
#include "esp32c5/rom/rtc.h"
#include "hal/misc.h"
#include "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
@@ -420,6 +423,22 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
}
/**
* @brief Enable or disable the soc root clock auto gating logic
*
* @param ena true to enable, false to disable
*/
static inline __attribute__((always_inline)) void clk_ll_soc_root_clk_auto_gating_bypass(bool ena)
{
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
if (ena) {
REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
} else {
REG_SET_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
}
}
}
/**
* @brief Select the clock source for RTC_SLOW_CLK
*