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	Merge branch 'feature/remove_hspi_macor_on_chips_later_than_s2_v4.3' into 'release/v4.3'
spi: remove hspi macor on chips later than s2 (v4.3) See merge request espressif/esp-idf!12956
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		@@ -38,10 +38,9 @@ typedef enum {
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    PERIPH_UHCI1_MODULE,
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    PERIPH_RMT_MODULE,
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    PERIPH_PCNT_MODULE,
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    PERIPH_SPI_MODULE,  //SPI1
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    PERIPH_FSPI_MODULE, //SPI2
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    PERIPH_HSPI_MODULE, //SPI3
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    PERIPH_VSPI_MODULE, //SPI4
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    PERIPH_SPI_MODULE,
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    PERIPH_SPI2_MODULE,
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    PERIPH_SPI3_MODULE,
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    PERIPH_SDMMC_MODULE,
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    PERIPH_TWAI_MODULE,
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    PERIPH_RNG_MODULE,
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@@ -84,8 +83,7 @@ typedef enum {
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    ETS_SPI1_INTR_SOURCE,                       /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
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    ETS_SPI2_INTR_SOURCE,                       /**< interrupt of SPI2, level*/
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    ETS_SPI3_INTR_SOURCE,                       /**< interrupt of SPI3, level*/
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    ETS_SPI4_INTR_SOURCE,                       /**< interrupt of SPI4, level*/
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    ETS_LCD_CAM_INTR_SOURCE,                    /**< interrupt of LCD camera, level*/
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    ETS_LCD_CAM_INTR_SOURCE = 24,               /**< interrupt of LCD camera, level*/
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    ETS_I2S0_INTR_SOURCE,                       /**< interrupt of I2S0, level*/
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    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
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    ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
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@@ -108,8 +106,7 @@ typedef enum {
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    ETS_I2C_EXT1_INTR_SOURCE,                   /**< interrupt of I2C controller0, level*/
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    ETS_SPI2_DMA_INTR_SOURCE,                   /**< interrupt of SPI2 DMA, level*/
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    ETS_SPI3_DMA_INTR_SOURCE,                   /**< interrupt of SPI3 DMA, level*/
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    ETS_SPI4_DMA_INTR_SOURCE,                   /**< interrupt of SPI4 DMA, level*/
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    ETS_WDT_INTR_SOURCE,                        /**< will be cancelled*/
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    ETS_WDT_INTR_SOURCE = 47,                   /**< will be cancelled*/
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    ETS_TIMER1_INTR_SOURCE = 48,
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    ETS_TIMER2_INTR_SOURCE,
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@@ -22,12 +22,12 @@
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#define SPI_IOMUX_PIN_NUM_MISO  31
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#define SPI_IOMUX_PIN_NUM_WP    28
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#define FSPI_FUNC_NUM           4
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#define FSPI_IOMUX_PIN_NUM_HD   9
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#define FSPI_IOMUX_PIN_NUM_CS   10
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#define FSPI_IOMUX_PIN_NUM_MOSI 11
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#define FSPI_IOMUX_PIN_NUM_CLK  12
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#define FSPI_IOMUX_PIN_NUM_MISO 13
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#define FSPI_IOMUX_PIN_NUM_WP   14
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#define SPI2_FUNC_NUM           4
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#define SPI2_IOMUX_PIN_NUM_HD   9
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#define SPI2_IOMUX_PIN_NUM_CS   10
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#define SPI2_IOMUX_PIN_NUM_MOSI 11
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#define SPI2_IOMUX_PIN_NUM_CLK  12
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#define SPI2_IOMUX_PIN_NUM_MISO 13
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#define SPI2_IOMUX_PIN_NUM_WP   14
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//HSPI have no iomux pins
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//SPI3 have no iomux pins
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