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Merge branch 'bugfix/spi_bus_unify_defualt_mosi_level_v5.1' into 'release/v5.1'

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spi: unify default mosi level on all targets (v5.1)

See merge request espressif/esp-idf!25014
This commit is contained in:
morris
2023-08-17 10:13:05 +08:00
parent 461db723f1 7a30edc412
commit 77b74ab091
10 changed files with 163 additions and 100 deletions
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41
components/hal/esp32c3/include/hal/spi_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -40,6 +40,7 @@ extern "C" {
#define SPI_LL_DMA_MAX_BIT_LEN (1 << 18) //reg len: 18 bits
#define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words
#define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized
/**
* The data structure holding calculated clock configuration. Since the
@@ -185,6 +186,27 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
hw->slave.slave_mode = 1;
}
/**
* Determine and unify the default level of mosi line when bus free
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
}
/**
* Apply the register configurations and wait until it's done
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_apply_config(spi_dev_t *hw)
{
hw->cmd.update = 1;
while (hw->cmd.update); //waiting config applied
}
/**
* Check whether user-defined transaction is done.
*
@@ -198,24 +220,11 @@ static inline bool spi_ll_usr_is_done(spi_dev_t *hw)
}
/**
* Trigger start of user-defined transaction for master.
* The synchronization between two clock domains is required in ESP32-S3
* Trigger start of user-defined transaction.
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_master_user_start(spi_dev_t *hw)
{
hw->cmd.update = 1;
while (hw->cmd.update);
hw->cmd.usr = 1;
}
/**
* Trigger start of user-defined transaction for slave.
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_slave_user_start(spi_dev_t *hw)
static inline void spi_ll_user_start(spi_dev_t *hw)
{
hw->cmd.usr = 1;
}