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esp32: fix RTC watchdog configuration in esp_restart

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RTC watchdog didn’t have any actions configured for any of the stages.
This change configures it to use SW_SYSTEM_RESET at stage 0 and a
full reset at stage 1. The timeout is now calculated based on
RTC_SLOW_CLK frequency.
This commit is contained in:
Ivan Grokhotkov
2017-07-10 16:36:56 +08:00
parent cbe23147bf
commit 780569c04a
2 changed files with 5 additions and 2 deletions
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components/soc/esp32/include/soc/rtc_cntl_reg.h
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@@ -1718,6 +1718,7 @@
#define RTC_WDT_STG_SEL_INT 1
#define RTC_WDT_STG_SEL_RESET_CPU 2
#define RTC_WDT_STG_SEL_RESET_SYSTEM 3
#define RTC_WDT_STG_SEL_RESET_RTC 4
#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90)
/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */