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Merge branch 'bugfix/flash_suspend_restriction' into 'master'

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spi_flash: make suspend off by default and add more information for using suspend

See merge request espressif/esp-idf!12812
This commit is contained in:
Michael (XIAO Xufeng)
2021-03-29 04:47:34 +00:00
parent 972d858409 c54ea54d98
commit 78090d24e4
9 changed files with 37 additions and 49 deletions
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12
docs/en/api-reference/storage/auto_suspend.inc
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@@ -3,6 +3,18 @@
When auto suspend is enabled
----------------------------
.. important::
The flash chip you are using must have suspend/resume function, even then, and not all flash chips with suspend/resume support auto-suspend on {IDF_TARGET_NAME}. If you use suspend feature on a unsupported chip, it may cause a severe crash. Therefore, we strongly suggest you reading the flash chip datasheets first. Ensure the flash chip satisfies the following conditions at minimum. Even then, thorough testing is recommended.
1. SUS bit in status registers should in SR2 bit7 (or SR bit15)(This is caused by the restriction of out software implementation).
2. Suspend command is 75H, resume command is 7AH(This is caused by the restriction of out software implementation).
3. When the flash is successfully suspended, all address of the flash, except from the section/block being erased, can be read correctly. And resume can be sent immediately at this state.
4. When the flash is successfully resumed, another suspend can be sent immediately at this state.
When auto suspend is enabled, the cache will be kept enabled while accessing the SPI1 bus (e.g. erasing/writing/reading main flash). The hardware handles the arbitration between them.
If SPI1 operation is short (like reading operation), the CPU and the cache will wait until the SPI1 operation is done. However if it's an erasing, auto suspend will happen, interrupting the erasing, making the CPU able to read from cache in limited time.